Cyrus Tsui

Person

Vancouver, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delay-matched ASIC conversion of a programmable logic device
- Patent number 7,038,490
- Issue date May 2, 2006
- Lattice Semiconductor Corporation
- Satwant Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with enhanced wide input product term cas...
- Patent number 6,903,573
- Issue date Jun 7, 2005
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-volatile and reconfigurable programmable logic devices
- Patent number 6,828,823
- Issue date Dec 7, 2004
- Lattice Semiconductor Corporation
- Cyrus Tsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device and method with generic logic blocks
- Patent number 6,765,408
- Issue date Jul 20, 2004
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device
- Patent number 6,462,576
- Issue date Oct 8, 2002
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Simultaneous wired and wireless remote in-system programming of mul...
- Patent number 6,389,321
- Issue date May 14, 2002
- Lattice Semiconductor Corporation
- Howard S. Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure dynamic in-system programming
- Patent number 6,356,107
- Issue date Mar 12, 2002
- Lattice Semiconductor Corporation
- Howard Y. M. Tang
- G01 - MEASURING TESTING
Information Patent Grant
Method and structure for dynamic in-system programming
- Patent number 6,304,099
- Issue date Oct 16, 2001
- Lattice Semiconductor Corporation
- Howard Y. M. Tang
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic device
- Patent number 6,294,925
- Issue date Sep 25, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for minimizing instantaneous currents when driving bus signals
- Patent number 6,278,311
- Issue date Aug 21, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device
- Patent number 6,255,847
- Issue date Jul 3, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuit device with slew control and skew c...
- Patent number 6,229,336
- Issue date May 8, 2001
- Lattice Semiconductor Corporation
- Bradley Felton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Combination of global clock and localized clocks
- Patent number 6,191,609
- Issue date Feb 20, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combination of global clock and localized clocks
- Patent number 6,133,750
- Issue date Oct 17, 2000
- Lattice Semiconductor Corp.
- Albert Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device
- Patent number 6,104,207
- Issue date Aug 15, 2000
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable output voltage levels
- Patent number 6,066,977
- Issue date May 23, 2000
- Lattice Semiconductor Corporation
- Bradley Felton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
In-system programmable interconnect circuit
- Patent number 6,034,541
- Issue date Mar 7, 2000
- Lattice Semiconductor Corporation
- Stanley J. Kopec
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequential and simultaneous manufacturing programming of multiple i...
- Patent number 6,023,570
- Issue date Feb 8, 2000
- Lattice Semiconductor Corp.
- Howard Y. M. Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application specific modules in a programmable logic device
- Patent number 5,835,405
- Issue date Nov 10, 1998
- Lattice Semiconductor Corporation
- Cyrus Y. Tsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output enable structure and method for a programmable logic device
- Patent number 5,506,517
- Issue date Apr 9, 1996
- Lattice Semiconductor Corporation
- Cyrus Y. Tsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplexed control pins for in-system programming and boundary sca...
- Patent number 5,412,260
- Issue date May 2, 1995
- Lattice Semiconductor Corporation
- Cyrus Y. Tsui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input routing pool
- Patent number 5,404,055
- Issue date Apr 4, 1995
- Lattice Semiconductor Corporation
- Kapil Shankar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure and method for implementing hierarchical routing pools in...
- Patent number 5,394,033
- Issue date Feb 28, 1995
- Lattice Semiconductor Corporation
- Cyrus Y. Tsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Arrangement for parallel programming of in-system programmable IC l...
- Patent number 5,329,179
- Issue date Jul 12, 1994
- Lattice Semiconductor Corporation
- Howard Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output logic macrocell with enhanced functional capabilities
- Patent number 5,191,243
- Issue date Mar 2, 1993
- Lattice Semiconductor Corporation
- Ju Shen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device providing product term sharing and steeri...
- Patent number 5,130,574
- Issue date Jul 14, 1992
- Lattice Semiconductor Corporation
- Ju Shen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Short detector for PROMS
- Patent number 4,701,695
- Issue date Oct 20, 1987
- Monolithic Memories, Inc.
- Albert Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Output circuit for a programmable logic array
- Patent number 4,684,830
- Issue date Aug 4, 1987
- Monolithic Memories, Inc.
- Cyrus Tsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Short detector for fusible link array using a pair of parallel conn...
- Patent number 4,670,708
- Issue date Jun 2, 1987
- Monolithic Memories, Inc.
- Bob Bosnyak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and structure for disabling and replacing defective memory i...
- Patent number 4,654,830
- Issue date Mar 31, 1987
- Monolithic Memories, Inc.
- H. T. Chua
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Device and method with generic logic blocks
- Publication number 20040000928
- Publication date Jan 1, 2004
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SIMULTANEOUS WIRED AND WIRELESS REMOTE IN-SYSTEM PROGRAMMING OF MUL...
- Publication number 20010041943
- Publication date Nov 15, 2001
- HOWARD Y. TANG
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Delay-matched ASIC conversion of a programmable logic device

Programmable logic device with enhanced wide input product term cas...

Non-volatile and reconfigurable programmable logic devices

Device and method with generic logic blocks

Programmable logic device

Simultaneous wired and wireless remote in-system programming of mul...

Method and structure dynamic in-system programming

Method and structure for dynamic in-system programming

Programmable logic device

Method for minimizing instantaneous currents when driving bus signals

Programmable logic device

Programmable integrated circuit device with slew control and skew c...

Combination of global clock and localized clocks

Combination of global clock and localized clocks

Programmable logic device

Programmable output voltage levels

In-system programmable interconnect circuit

Sequential and simultaneous manufacturing programming of multiple i...

Application specific modules in a programmable logic device

Output enable structure and method for a programmable logic device

Multiplexed control pins for in-system programming and boundary sca...

Input routing pool

Structure and method for implementing hierarchical routing pools in...

Arrangement for parallel programming of in-system programmable IC l...

Output logic macrocell with enhanced functional capabilities

Programmable logic device providing product term sharing and steeri...

Short detector for PROMS

Output circuit for a programmable logic array

Short detector for fusible link array using a pair of parallel conn...

Method and structure for disabling and replacing defective memory i...

Patents Applicationslast 30 patents

Device and method with generic logic blocks

SIMULTANEOUS WIRED AND WIRELESS REMOTE IN-SYSTEM PROGRAMMING OF MUL...