Daiki Komatsu

Person

Beppu, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer chip scale package
- Patent number 12,057,417
- Issue date Aug 6, 2024
- Texas Instruments Incorporated
- Masamitsu Matsuura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with pre-wetted contact sidewall surfaces
- Patent number 11,217,513
- Issue date Jan 4, 2022
- Texas Instruments Incorporated
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages with wettable flanks and methods of man...
- Patent number 11,062,980
- Issue date Jul 13, 2021
- Texas Instruments Incorporated
- Makoto Shibuya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with pre-wetted contact sidewall surfaces
- Patent number 10,636,729
- Issue date Apr 28, 2020
- Texas Instruments Incorporated
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed repassivation for wafer chip scale packaging
- Patent number 10,541,220
- Issue date Jan 21, 2020
- Texas Instruments Incorporated
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ELECTRONIC DEVICE WITH A REINFORCING LAYER
- Publication number 20240395731
- Publication date Nov 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Masamitsu Matsuura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER CHIP SCALE PACKAGE
- Publication number 20240379597
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Masamitsu Matsuura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE ISOLATION WITH CONFORMAL COATING
- Publication number 20240363465
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Anindya Poddar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHIELDED LEAD PACKAGE FOR HIGH VOLTAGE DEVICES
- Publication number 20240290676
- Publication date Aug 29, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Masamitsu Matsuura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hall Sensor Using Face Down Structure with Through Substrate Vias
- Publication number 20240210497
- Publication date Jun 27, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- G01 - MEASURING TESTING
Information Patent Application
SENSOR PACKAGE WITH LOW ASPECT RATIO THROUGH SILICON VIA
- Publication number 20240178164
- Publication date May 30, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Masamitsu Matsuura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEADFRAME BASED POWER MODULE
- Publication number 20240178104
- Publication date May 30, 2024
- TEXAS INSTRUMENTS INCORPORATED
- MAKOTO SHIBUYA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LASING TO ATTACH DIE TO LEAD FRAME
- Publication number 20240145419
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Daiki KOMATSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SENSOR WITH TSV STRUCTURE
- Publication number 20240145454
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- DAIKI KOMATSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION PACKAGE WITH HIGH THERMAL CONDUCTIVITY
- Publication number 20230317568
- Publication date Oct 5, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SENSOR PACKAGE WITH CAVITY CREATED USING SACRIFICIAL MATERIAL
- Publication number 20230253281
- Publication date Aug 10, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER CHIP SCALE PACKAGE
- Publication number 20210111136
- Publication date Apr 15, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Masamitsu Matsuura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REPASSIVATION APPLICATION FOR WAFER-LEVEL CHIP-SCALE PACKAGE
- Publication number 20200388508
- Publication date Dec 10, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Makoto Shibuya
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
Integrated Circuit Package With Pre-Wetted Contact Sidewall Surfaces
- Publication number 20200286816
- Publication date Sep 10, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRINTED REPASSIVATION FOR WAFER CHIP SCALE PACKAGING
- Publication number 20200043878
- Publication date Feb 6, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER CHIP SCALE PACKAGING WITH BALL ATTACH BEFORE REPASSIVATION
- Publication number 20200043778
- Publication date Feb 6, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES WITH WETTABLE FLANKS AND METHODS OF MAN...
- Publication number 20190206768
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Makoto Shibuya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Package with Pre-wetted Contact Sidewall Surfaces
- Publication number 20180366396
- Publication date Dec 20, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLATED DITCH PRE-MOLD LEAD FRAME, SEMICONDUCTOR PACKAGE, AND METHOD...
- Publication number 20180122731
- Publication date May 3, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS

Daiki Komatsu

Person

Patents Grantslast 30 patents

Wafer chip scale package

Integrated circuit package with pre-wetted contact sidewall surfaces

Integrated circuit packages with wettable flanks and methods of man...

Integrated circuit package with pre-wetted contact sidewall surfaces

Printed repassivation for wafer chip scale packaging

Patents Applicationslast 30 patents

ELECTRONIC DEVICE WITH A REINFORCING LAYER

WAFER CHIP SCALE PACKAGE

DIE ISOLATION WITH CONFORMAL COATING

SHIELDED LEAD PACKAGE FOR HIGH VOLTAGE DEVICES

Hall Sensor Using Face Down Structure with Through Substrate Vias

SENSOR PACKAGE WITH LOW ASPECT RATIO THROUGH SILICON VIA

LEADFRAME BASED POWER MODULE

LASING TO ATTACH DIE TO LEAD FRAME

OPTICAL SENSOR WITH TSV STRUCTURE

ISOLATION PACKAGE WITH HIGH THERMAL CONDUCTIVITY

SENSOR PACKAGE WITH CAVITY CREATED USING SACRIFICIAL MATERIAL

WAFER CHIP SCALE PACKAGE

REPASSIVATION APPLICATION FOR WAFER-LEVEL CHIP-SCALE PACKAGE

Integrated Circuit Package With Pre-Wetted Contact Sidewall Surfaces

PRINTED REPASSIVATION FOR WAFER CHIP SCALE PACKAGING

WAFER CHIP SCALE PACKAGING WITH BALL ATTACH BEFORE REPASSIVATION

INTEGRATED CIRCUIT PACKAGES WITH WETTABLE FLANKS AND METHODS OF MAN...

Integrated Circuit Package with Pre-wetted Contact Sidewall Surfaces

PLATED DITCH PRE-MOLD LEAD FRAME, SEMICONDUCTOR PACKAGE, AND METHOD...