Patent Application
20210111136
This Disclosure relates to wafer chip scale packages having at least one redistribution layer.
A wafer chip scale package (WCSP), or CSP, is a type of integrated circuit (IC) package, which is a variant of the flip-chip interconnection technique where all packaging is implemented at the wafer level. The needed metal interconnect and the dielectric layers over the metal interconnect layers are applied on top of a wafer using photolithographic techniques that fit well with conventional wafer processing. These layers are typically thin, and a semiconductor die generally forms major portion of the package body. All the interconnects between the semiconductor die, the package, and the user's printed circuit board (PCB) are on the active side (top side) of the semiconductor die.
A redistribution layer (RDL) is formed from a process that generally involves one or two layers of metal and two or three layers of a polymer dielectric material, such as polyimide or benzocyclobutene (BCB). WLCSPs can be categorized into two different construction types, being a direct bump type and an RDL type. RDL technology allows a semiconductor die designed for wire bonding with bond pads connected to nodes in the circuitry all arranged along the periphery of the die, to be converted into a WCSP that has solder bump pads attributed throughout the area of the die.
In the case of the RDL type WCSP, multiple photolithography steps are used to form the solder bump pads for receiving the solder balls. These photolithography steps generally include forming at least one patterned RDL that includes bump pads that are lateral to the bond pads coupled together by RDL traces, a patterned re-passivation layer such as a polyimide (PI) layer on the RDL that exposes the bump pads, and then a patterned under bump metallization (UBM) layer is formed on the bump pads. A conventional WCSP thus requires three separate photolithography steps to form the solder bump pads.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
Disclosed aspects recognize conventional RDL type WCSPs can benefit from tighter process control of the solder bump pads that may provide a yield enhancement. As described above in the Background, conventional RDL type WCSPs generally require three separate photolithography process steps for forming the solder bump pads. This conventional multiple photolithography step process flow results in assembly yield loss including losses due to electrical shorts resulting from seed layer residue.
Disclosed aspects include a dielectric ring, such as comprising solder resist, a polyimide, or an epoxy. Disclosed dielectric rings can be formed directly on the RDL bump pads without photolithography by additively depositing (e.g. inkjet printing, or screen printing) a ring of dielectric material on the bump pads in the step before the solder ball attach (or drop). The resulting dielectric ringed bump pads are referred to herein as a ‘dielectric ringed solder bump pads.’ Printing a disclosed dielectric ring on the bump pads to form disclosed dielectric ringed solder bump pads eliminates two of the three conventionally needed photolithography steps for forming RDL type WCSPs, eliminating the photolithography step for UBM formation on the bump pad, and the photolithography step for forming the patterned re-passivation layer on the RDL including on the periphery of the bump pad.
Accordingly, disclosed dielectric ringed solder bump pads can be formed from only one photolithography step, that being for the electroplating process to form the patterned RDL. As used herein, a ‘ring’ means an enclosed shape or the outline of an enclosed shape, such as substantially circular including elliptical, rectangular, or square. Disclosed rings can be fully continuous lines or curves, and can also be configured as a dashed-line comprising a plurality of spaced apart segments. Disclosed methods for forming disclosed dielectric ringed solder bump pads for RDL type WCSPs thus simplifies the conventional process flow for forming solder bump pads for RDL type WCSPs to provide a reduced cost solution by substituting a dielectric ring that can be additively deposited for two conventionally required photolithography process steps for forming solder bumps.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example aspects are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this Disclosure.
RDL WCSP 100 includes a substrate 102 comprising a semiconductor surface layer including circuitry 180 configured for at least one function having at least a top metal interconnect layer 168 thereon that includes at least one bond pad 181 coupled to a node in the circuitry 180. There is a passivation layer 176 having a passivation aperture for exposing the bond pad 181 on the top metal interconnect layer 168. The RDL 160 that generally comprises copper or a copper alloy and as shown includes a bump pad 160b coupled by a trace 160a that is shown coupled to metal filled plugs 184 (e.g., W plugs) through a passivation layer 176 to the bond pad 181. The passivation layer 176 although shown as a single layer, can also comprise two or more layers.
The solder ball 195 (e.g., about 200 μm in diameter) is on the UBM layer 167. The circuitry 180 comprises circuit elements (including transistors, and generally diodes, resistors, capacitors, etc.) that can be directly formed in the substrate 102 or can be formed in the epitaxial layer of a bulk substrate such as comprising silicon, where the circuitry 180 is configured together for generally realizing at least one circuit function. Example circuit functions include analog (e.g., amplifier or power converter), radio frequency (RF), digital, or non-volatile memory functions.
RDL WCSP 150 includes a substrate 102 comprising a semiconductor surface layer including circuitry 180 configured for at least one function having at least a top metal interconnect layer 168 thereon that includes at least one bond pad 181 coupled to a node in the circuitry 180. As with RDL WCSP 100 RDL, for WCSP 150 the RDL 160 includes a bump pad 160b coupled by a trace 160a shown coupled to metal filled plugs 184, such as W plugs, that provide coupling through the passivation layer 176 to the bond pad 181.
A solder ball 195 is directly on the bump pad 160b, so it can be seen there is no conventional UBM layer on the bump pad 160b. The dielectric ring 172 is on the bump pad 160b which has an inner area (e.g., inner diameter) in physical contact with the solder ball 195.
The re-passivation layer 192 generally comprises a dielectric layer such as a mold material that is epoxy-based which is positioned over the dielectric ring 172 and as noted above is in physical contact with the solder ball 195. A typical re-passivation layer 192 thickness is 75 μm to 150 μm, such as 100 μm to 125 μm thick.
As seen in the cross-sectional view, the RDL 160 is on a passivation layer 176 that has metal filled plugs 184, such as W plugs, that are completely through a thickness of the passivation layer 176 to couple to bond pads shown in
Disclosed aspects can be integrated into a variety of assembly flows to form a variety of different WCSP devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.
Those skilled in the art to which this Disclosure relates will appreciate that many variations of disclosed aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the above-described aspects without departing from the scope of this Disclosure.
This application claims the benefit of Provisional Application Ser. No. 62/915,572 entitled “Wafer Scale Electronic Device,” filed on Oct. 15, 2019, which is herein incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62915572 | Oct 2019 | US |
