Daniel Rodko

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Testing bit write operation to a memory array in integrated circuits
- Patent number 11,657,887
- Issue date May 23, 2023
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Grant
Microchip level shared array repair
- Patent number 11,462,295
- Issue date Oct 4, 2022
- International Business Machines Corporation
- Timothy Meehan
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test for bit-write enabled memory arrays
- Patent number 10,998,075
- Issue date May 4, 2021
- International Business Machines Corporation
- William Huott
- G11 - INFORMATION STORAGE
Information Patent Grant
Sequential error capture during memory test
- Patent number 10,971,242
- Issue date Apr 6, 2021
- International Business Machines Corporation
- William Huott
- G11 - INFORMATION STORAGE
Information Patent Grant
Power saving scannable latch output driver
- Patent number 10,890,623
- Issue date Jan 12, 2021
- International Business Machines Corporation
- William Huott
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,593,420
- Issue date Mar 17, 2020
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip hardware-controlled window strobing
- Patent number 10,288,684
- Issue date May 14, 2019
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Grant
On-chip hardware-controlled window strobing
- Patent number 10,281,527
- Issue date May 7, 2019
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,170,199
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,079,070
- Issue date Sep 18, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Partition-able storage of test results using inactive storage elements
- Patent number 9,983,261
- Issue date May 29, 2018
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Grant
Multi-match error detection in content addressable memory testing
- Patent number 9,697,910
- Issue date Jul 4, 2017
- International Business Machines Corporation
- William V. Huott
- G11 - INFORMATION STORAGE
Information Patent Grant
Shift register with opposite shift data and shift clock directions
- Patent number 9,627,012
- Issue date Apr 18, 2017
- International Business Machines Corporation
- William V. Huott
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory testing system
- Patent number 8,327,207
- Issue date Dec 4, 2012
- International Business Machines Corporation
- Kevin J. Duffy
- G11 - INFORMATION STORAGE
Information Patent Grant
BIST address generation architecture for multi-port memories
- Patent number 7,536,613
- Issue date May 19, 2009
- International Business Machines Corporation
- William Vincent Huott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merged MISR and output register without performance impact for circ...
- Patent number 7,478,297
- Issue date Jan 13, 2009
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Merged MISR and output register without performance impact for circ...
- Patent number 7,305,602
- Issue date Dec 4, 2007
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock duty cycle based access timer combined with standard stage cl...
- Patent number 7,275,194
- Issue date Sep 25, 2007
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Grant
Array self repair using built-in self test techniques
- Patent number 7,257,745
- Issue date Aug 14, 2007
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TESTING BIT WRITE OPERATION TO A MEMORY ARRAY IN INTEGRATED CIRCUITS
- Publication number 20230089274
- Publication date Mar 23, 2023
- International Business Machines Corporation
- Thomas J. KNIPS
- G11 - INFORMATION STORAGE
Information Patent Application
MICROCHIP LEVEL SHARED ARRAY REPAIR
- Publication number 20210319845
- Publication date Oct 14, 2021
- International Business Machines Corporation
- Timothy MEEHAN
- G11 - INFORMATION STORAGE
Information Patent Application
SEQUENTIAL ERROR CAPTURE DURING MEMORY TEST
- Publication number 20210074375
- Publication date Mar 11, 2021
- International Business Machines Corporation
- William Huott
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF-TEST FOR BIT-WRITE ENABLED MEMORY ARRAYS
- Publication number 20210074376
- Publication date Mar 11, 2021
- International Business Machines Corporation
- William Huott
- G11 - INFORMATION STORAGE
Information Patent Application
ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING
- Publication number 20180364309
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING
- Publication number 20180364308
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180174666
- Publication date Jun 21, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180151248
- Publication date May 31, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180114585
- Publication date Apr 26, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
PARTITION-ABLE STORAGE OF TEST RESULTS USING INACTIVE STORAGE ELEMENTS
- Publication number 20170350940
- Publication date Dec 7, 2017
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Application
MEMORY TESTING SYSTEM
- Publication number 20110307747
- Publication date Dec 15, 2011
- International Business Machines Corporation
- Kevin J. Duffy
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY
- Publication number 20110296259
- Publication date Dec 1, 2011
- International Business Machines Corporation
- Bargav Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Merged MISR and Output Register Without Performance Impact for Circ...
- Publication number 20080059854
- Publication date Mar 6, 2008
- International Business Machines Corporation
- Yuen H. Chan
- G01 - MEASURING TESTING
Information Patent Application
Merged MISR and output register without performance impact for circ...
- Publication number 20060195738
- Publication date Aug 31, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G01 - MEASURING TESTING
Information Patent Application
Clock duty cycle based access timer combined with standard stage cl...
- Publication number 20060195740
- Publication date Aug 31, 2006
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Application
Array self repair using built-in self test techniques
- Publication number 20060174175
- Publication date Aug 3, 2006
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Application
BIST address generation architecture for multi-port memories
- Publication number 20050268167
- Publication date Dec 1, 2005
- International Business Machines Corporation
- William Vincent Huott
- G06 - COMPUTING CALCULATING COUNTING

Daniel Rodko

Person

Patents Grantslast 30 patents

Testing bit write operation to a memory array in integrated circuits

Microchip level shared array repair

Built-in self-test for bit-write enabled memory arrays

Sequential error capture during memory test

Power saving scannable latch output driver

Testing content addressable memory and random access memory

On-chip hardware-controlled window strobing

On-chip hardware-controlled window strobing

Testing content addressable memory and random access memory

Testing content addressable memory and random access memory

Partition-able storage of test results using inactive storage elements

Multi-match error detection in content addressable memory testing

Shift register with opposite shift data and shift clock directions

Memory testing system

BIST address generation architecture for multi-port memories

Merged MISR and output register without performance impact for circ...

Merged MISR and output register without performance impact for circ...

Clock duty cycle based access timer combined with standard stage cl...

Array self repair using built-in self test techniques

Patents Applicationslast 30 patents

TESTING BIT WRITE OPERATION TO A MEMORY ARRAY IN INTEGRATED CIRCUITS

MICROCHIP LEVEL SHARED ARRAY REPAIR

SEQUENTIAL ERROR CAPTURE DURING MEMORY TEST

BUILT-IN SELF-TEST FOR BIT-WRITE ENABLED MEMORY ARRAYS

ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING

ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

PARTITION-ABLE STORAGE OF TEST RESULTS USING INACTIVE STORAGE ELEMENTS

MEMORY TESTING SYSTEM

TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY

Merged MISR and Output Register Without Performance Impact for Circ...

Merged MISR and output register without performance impact for circ...

Clock duty cycle based access timer combined with standard stage cl...

Array self repair using built-in self test techniques

BIST address generation architecture for multi-port memories