Patent Application
20110296259
The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and structure for simultaneously testing both memory arrays and associated logic using Array Built-In Self Test (ABIST) circuitry.
During the manufacture of semiconductors on wafers, an important aspect of the manufacturing process is to test the circuitry to determine if the configuration is correct. In order to determine if the circuitry is correct, certain test circuitry is employed. The test circuitry determines if there were any errors or anomalies during manufacturing.
Typically, test patterns are input into the circuits on the wafers. If the configuration is correct, then specific output patterns will be produced. Otherwise, the output patterns will be inconsistent with predetermined output patterns to indicate errors. The output patterns can also be used to extrapolate potential problems for future usage or continual problems in the manufacturing process.
Testing the on-chip circuitry, however, requires testing of multiple aspects of the circuitry. For example, testing of array macros can be performed by Array Built-In Self Test (ABIST) circuitry. ABIST circuitry is additional on-chip circuitry that is coupled to an ABIST test engine that allows for screening of mature technology. Additionally, the ABIST test engines have contingency protocols for early hardware screening and failure analysis.
Test engines, such as the ABIST test engines, however, do not typically provide a full complement of analyses for all of the circuitry associated with the integrated circuit memory device. As a result, logic contained with an array macro may not be fully tested by on-chip test circuitry and the associated test engines. To compensate for the lack of analysis for logic within the array macro, Logic Built-In Self Tests (LBISTs) are also employed to increase coverage of the logic within the array macro. Typically, LBIST results are captured into scannable latches to verify correct behavior.
A traditional method for testing Static Random Access Memories (SRAMs) with logic is to test the SRAM cells with ABIST and use LBIST to test the remaining logic (e.g., hit logic, multiplexers, etc.) downstream from the array. However, during LBIST, the SRAM portion of the macro is in “write-through” mode. As a result, read patterns are not included in the LBIST, thus limiting test coverage.
In an exemplary embodiment, a method of testing an integrated circuit device, the integrated circuit device having a memory array portion and a logic portion, includes providing test data to the memory array portion of the integrated circuit device using Array Built-In Self Test (ABIST) circuitry; and simultaneously testing the logic portion of the integrated circuit device using the ABIST circuitry, wherein both the memory array portion and the logic portion of the integrated circuit device are tested at speed.
In another embodiment, a method of testing a static random access memory (SRAM) macro having an SRAM array portion and a logic portion includes providing test data to the SRAM array portion of the SRAM macro using Array Built-In Self Test (ABIST) circuitry; and simultaneously testing the logic portion of the SRAM macro using the ABIST circuitry, wherein both the SRAM array portion and the logic portion of the SRAM macro are tested at speed.
In another embodiment, an integrated circuit device includes a memory array portion and a logic portion; an Array Built-In Self Test (ABIST) engine configured to provide ABIST data to the memory array portion; and a Logic Built-In Self Test (LBIST) engine configured to provide LBIST data to the logic portion; wherein the ABIST engine is further configured to selectively provide ABIST data to the logic portion so as to simultaneously test the memory array and logic portions of the integrated circuit device at speed.
In still another embodiment, a static random access memory (SRAM) macro device includes an SRAM array portion and a logic portion; an Array Built-In Self Test (ABIST) engine configured to provide ABIST data to the SRAM array portion; and a Logic Built-In Self Test (LBIST) engine configured to provide LBIST data to the logic portion; wherein the ABIST engine is further configured to selectively provide ABIST data to the logic portion so as to simultaneously test the SRAM array and logic portions of the SRAM macro device at speed.
Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
Disclosed herein is a method and structure for simultaneously testing, at speed, both memory arrays (e.g., SRAM) and associated logic using ABIST circuitry. In brief, the simultaneous testing is implemented using a single pass/fail compare latch, as well as an ABIST multiplexer (MUX) to uniquely test each memory cell (with another compare latch) to isolate the fail to the SRAM or to the downstream logic. In so doing, both the SRAM and hit logic are tested together, thereby delivering greater test coverage than a traditional random LBIST method. The embodiments herein will provide, for example, a wide variety of multi-cycle read and write patterns versus traditional single-cycle, write-through LBIST patterns.
Referring initially to
In contrast,
Referring now to
In the case of the SRAM array 302, there are several (N) bits that are output therefrom. Thus, a specific output bit from the SRAM is selected via an N to 1 multiplexer 314. The selected bit is compared, using compare circuit 310a, with an ABIST SRAM bit compare signal (e.g., from the ABIST engine 104). In the case of the logic 304, the one bit output therefrom is compared, using compare circuit 310b, with an ABIST Logic bit compare signal (e.g., from the ABIST engine 104).
While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
