Daniel S. Reed

Person

Otsego, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bit set modes for a resistive sense memory cell array
- Patent number 8,934,281
- Issue date Jan 13, 2015
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory cell with resistive sense element block erase a...
- Patent number 8,213,259
- Issue date Jul 3, 2012
- Seagate Technology LLC
- Daniel S. Reed
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer memory device with multiple interfaces
- Patent number 8,194,437
- Issue date Jun 5, 2012
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Spin-torque bit cell with unpinned reference layer and unidirection...
- Patent number 8,098,538
- Issue date Jan 17, 2012
- Seagate Technology LLC
- Daniel Seymour Reed
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Computer memory device with status register
- Patent number 8,081,504
- Issue date Dec 20, 2011
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-stage parallel data transfer
- Patent number 8,045,412
- Issue date Oct 25, 2011
- Seagate Technology LLC
- Yong Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit set modes for a resistive sense memory cell array
- Patent number 8,040,713
- Issue date Oct 18, 2011
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive sense memory array with partial block update capability
- Patent number 7,944,731
- Issue date May 17, 2011
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Simultaneously writing multiple addressable blocks of user data to...
- Patent number 7,944,729
- Issue date May 17, 2011
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Spin-torque bit cell with unpinned reference layer and unidirection...
- Patent number 7,940,592
- Issue date May 10, 2011
- Seagate Technology LLC
- Daniel Seymour Reed
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Non-volatile memory array with resistive sense element block erase...
- Patent number 7,885,097
- Issue date Feb 8, 2011
- Seagate Technology LLC
- Daniel S. Reed
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive sense memory array with partial block update capability
- Patent number 7,830,700
- Issue date Nov 9, 2010
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-element magnetic memory cell
- Patent number 7,474,569
- Issue date Jan 6, 2009
- Honeywell International Inc.
- Daniel S. Reed
- G11 - INFORMATION STORAGE
Information Patent Grant
Complementary giant magneto-resistive memory with full-turn word line
- Patent number 7,426,133
- Issue date Sep 16, 2008
- Honeywell International, Inc.
- Owen J. Hynes
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for fabricating giant magnetoresistive (GMR) devices
- Patent number 7,383,626
- Issue date Jun 10, 2008
- Honeywell International Inc.
- Daniel L. Baseman
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM read sequence using canted bit magnetization
- Patent number 7,248,496
- Issue date Jul 24, 2007
- Honeywell International Inc.
- Romney R. Katti
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit end design for pseudo spin valve (PSV) devices
- Patent number 7,183,042
- Issue date Feb 27, 2007
- Honeywell International Inc.
- Romney R. Katti
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating giant magnetoresistive (GMR) devices
- Patent number 7,114,240
- Issue date Oct 3, 2006
- Honeywell International, Inc.
- Daniel L. Baseman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Bit Set Modes for a Resistive Sense Memory Cell Array
- Publication number 20120033482
- Publication date Feb 9, 2012
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirection...
- Publication number 20110205788
- Publication date Aug 25, 2011
- Seagate Technology LLC
- Daniel Seymour Reed
- G01 - MEASURING TESTING
Information Patent Application
Non-Volatile Memory Array With Resistive Sense Element Block Erase...
- Publication number 20110026305
- Publication date Feb 3, 2011
- Seagate Technology LLC
- Daniel S. Reed
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY
- Publication number 20110029714
- Publication date Feb 3, 2011
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Simultaneously Writing Multiple Addressable Blocks of User Data to...
- Publication number 20100188883
- Publication date Jul 29, 2010
- SEAGATE TECHNOLOGY LLC
- Yiran Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES
- Publication number 20100177562
- Publication date Jul 15, 2010
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Application
BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY
- Publication number 20100177551
- Publication date Jul 15, 2010
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirection...
- Publication number 20100135072
- Publication date Jun 3, 2010
- Seagate Technology LLC
- Daniel Seymour Reed
- G01 - MEASURING TESTING
Information Patent Application
RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY
- Publication number 20100118587
- Publication date May 13, 2010
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Stage Parallel Data Transfer
- Publication number 20100097841
- Publication date Apr 22, 2010
- Seagate Technology LLC
- Yong Lu
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTER MEMORY DEVICE WITH STATUS REGISTER
- Publication number 20100095050
- Publication date Apr 15, 2010
- Seagate Technology LLC
- Yiran Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Volatile Memory Array with Resistive Sense Element Block Erase...
- Publication number 20100091548
- Publication date Apr 15, 2010
- Seagate Technology LLC
- Daniel S. Reed
- G11 - INFORMATION STORAGE
Information Patent Application
Two-element magnetic memory cell
- Publication number 20070272036
- Publication date Nov 29, 2007
- Honeywell International Inc.
- Daniel S. Reed
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM read sequence using canted bit magnetization
- Publication number 20070109839
- Publication date May 17, 2007
- Honeywell International Inc.
- Romney R. Katti
- G11 - INFORMATION STORAGE
Information Patent Application
Giant magneto-resistive static read RAM memory architecture
- Publication number 20070091669
- Publication date Apr 26, 2007
- Honeywell International Inc.
- Owen J. Hynes
- G11 - INFORMATION STORAGE
Information Patent Application
Methods for fabricating giant magnetoresistive (GMR) devices
- Publication number 20060277747
- Publication date Dec 14, 2006
- Honeywell International, Inc.
- Daniel L. Baseman
- G11 - INFORMATION STORAGE
Information Patent Application
Method for fabricating giant magnetoresistive (GMR) devices
- Publication number 20050097725
- Publication date May 12, 2005
- Honeywell International Inc.
- Daniel L. Baseman
- G11 - INFORMATION STORAGE
Information Patent Application
Bit end design for pseudo spin valve (PSV) devices
- Publication number 20050101079
- Publication date May 12, 2005
- Honeywell International Inc.
- Romney R. Katti
- G11 - INFORMATION STORAGE

Daniel S. Reed

Person

Patents Grantslast 30 patents

Bit set modes for a resistive sense memory cell array

Non-volatile memory cell with resistive sense element block erase a...

Computer memory device with multiple interfaces

Spin-torque bit cell with unpinned reference layer and unidirection...

Computer memory device with status register

Multi-stage parallel data transfer

Bit set modes for a resistive sense memory cell array

Resistive sense memory array with partial block update capability

Simultaneously writing multiple addressable blocks of user data to...

Spin-torque bit cell with unpinned reference layer and unidirection...

Non-volatile memory array with resistive sense element block erase...

Resistive sense memory array with partial block update capability

Two-element magnetic memory cell

Complementary giant magneto-resistive memory with full-turn word line

Methods for fabricating giant magnetoresistive (GMR) devices

MRAM read sequence using canted bit magnetization

Bit end design for pseudo spin valve (PSV) devices

Method for fabricating giant magnetoresistive (GMR) devices

Patents Applicationslast 30 patents

Bit Set Modes for a Resistive Sense Memory Cell Array

Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirection...

Non-Volatile Memory Array With Resistive Sense Element Block Erase...

RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY

Simultaneously Writing Multiple Addressable Blocks of User Data to...

COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES

BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY

Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirection...

RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY

Multi-Stage Parallel Data Transfer

COMPUTER MEMORY DEVICE WITH STATUS REGISTER

Non-Volatile Memory Array with Resistive Sense Element Block Erase...

Two-element magnetic memory cell

MRAM read sequence using canted bit magnetization

Giant magneto-resistive static read RAM memory architecture

Methods for fabricating giant magnetoresistive (GMR) devices

Method for fabricating giant magnetoresistive (GMR) devices

Bit end design for pseudo spin valve (PSV) devices