Darin A. Chan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High-voltage devices integrated on semiconductor-on-insulator subst...
- Patent number 11,545,570
- Issue date Jan 3, 2023
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Pinghui Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Density-controllable dummy fill strategy for near-MRAM periphery an...
- Patent number 10,374,005
- Issue date Aug 6, 2019
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Pinghui Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetism-controllable dummy structures in memory device
- Patent number 9,698,200
- Issue date Jul 4, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Pinghui Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Body tie test structure for accurate body effect measurement
- Patent number 8,293,606
- Issue date Oct 23, 2012
- GLOBALFOUNDARIES, Inc.
- Sriram Madhavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Body tie test structure for accurate body effect measurement
- Patent number 7,880,229
- Issue date Feb 1, 2011
- GLOBALFOUNDRIES Inc.
- Sriram Madhavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for design of semiconductor circuits
- Patent number 7,861,195
- Issue date Dec 28, 2010
- Advanced Mirco Devices, Inc.
- Darin A. Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disposable spacer process for field effect transistor fabrication
- Patent number 7,494,885
- Issue date Feb 24, 2009
- Advanced Micro Devices, Inc.
- Mario M. Pelella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a semiconductor device on an SOI substrate
- Patent number 7,465,623
- Issue date Dec 16, 2008
- Advanced Micro Devices, Inc.
- Mario M. Pelella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and method of manufacture
- Patent number 7,276,755
- Issue date Oct 2, 2007
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectable open circuit and anti-fuse element
- Patent number 7,250,667
- Issue date Jul 31, 2007
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor component and method of manufacture
- Patent number 7,223,640
- Issue date May 29, 2007
- Advanced Micro Devices, Inc.
- Mario M. Pelella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conversion of transition metal to silicide through back end process...
- Patent number 7,151,020
- Issue date Dec 19, 2006
- Advanced Micro Devices, Inc.
- Jeffrey P. Patton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trenches to reduce lateral silicide growth in integrated circuit te...
- Patent number 7,023,059
- Issue date Apr 4, 2006
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectable open circuit and anti-fuse element, and fabrication meth...
- Patent number 7,015,076
- Issue date Mar 21, 2006
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning narrow gate lines
- Patent number 6,812,077
- Issue date Nov 2, 2004
- Advanced Micro Devices, Inc.
- Darin Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitride offset spacer to minimize silicon recess by using poly reox...
- Patent number 6,780,776
- Issue date Aug 24, 2004
- Advanced Micro Devices, Inc.
- Wen-Jie Qi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI device with different silicon thicknesses
- Patent number 6,764,917
- Issue date Jul 20, 2004
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing gate line deformation and reducing gate line wi...
- Patent number 6,764,947
- Issue date Jul 20, 2004
- Advanced Micro Devices, Inc.
- Darin Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing pattern deformation and photoresist poisoning i...
- Patent number 6,764,949
- Issue date Jul 20, 2004
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device using amorphous carbo...
- Patent number 6,750,127
- Issue date Jun 15, 2004
- Advanced Micro Devices, Inc.
- Mark S. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI device with wrap-around contact to underside of body, and metho...
- Patent number 6,566,176
- Issue date May 20, 2003
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for shallow trench isolation with removal of strained island...
- Patent number 6,521,510
- Issue date Feb 18, 2003
- Advanced Micro Devices, Inc.
- Philip Fisher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI device with wrap-around contact to underside of body, and metho...
- Patent number 6,441,435
- Issue date Aug 27, 2002
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor devices with trench isolation
- Patent number 6,403,492
- Issue date Jun 11, 2002
- Advanced Micro Devices, Inc.
- Matthew S. Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and arrangements for insulating local interconnects for imp...
- Patent number 6,399,480
- Issue date Jun 4, 2002
- Advanced Micro Devices, Inc.
- William G. En
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of a barrier layer for tungsten damascene interconnects b...
- Patent number 6,166,428
- Issue date Dec 26, 2000
- Advanced Micro Devices, Inc.
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elimination of residual materials in a multiple-layer interconnect...
- Patent number 6,153,933
- Issue date Nov 28, 2000
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating an integrated circuit including a tri-layer p...
- Patent number 6,127,261
- Issue date Oct 3, 2000
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Local interconnects for improved alignment tolerance and size reduc...
- Patent number 6,121,663
- Issue date Sep 19, 2000
- Advanced Micro Devices, Inc.
- William G. En
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multipurpose cap layer dielectric
- Patent number 6,114,235
- Issue date Sep 5, 2000
- Advanced Micro Devices, Inc.
- David K. Foote
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HIGH-VOLTAGE DEVICES INTEGRATED ON SEMICONDUCTOR-ON-INSULATOR SUBST...
- Publication number 20210210630
- Publication date Jul 8, 2021
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- PINGHUI LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DENSITY-CONTROLLABLE DUMMY FILL STRATEGY FOR NEAR-MRAM PERIPHERY AN...
- Publication number 20190206928
- Publication date Jul 4, 2019
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Pinghui LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETISM-CONTROLLABLE DUMMY STRUCTURES IN MEMORY DEVICE
- Publication number 20170104029
- Publication date Apr 13, 2017
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Pinghui LI
- G11 - INFORMATION STORAGE
Information Patent Application
BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
- Publication number 20110086484
- Publication date Apr 14, 2011
- GLOBALFOUNDRIES INC.
- Sriram MADHAVAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR DESIGN OF SEMICONDUCTOR CIRCUITS
- Publication number 20090193369
- Publication date Jul 30, 2009
- Advanced Micro Devices, Inc.
- Darin A. Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
- Publication number 20090101976
- Publication date Apr 23, 2009
- Advanced Micro Devices, Inc.
- Sriram MADHAVAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING AN SOI DEFINED SEMICONDUCTOR DEVICE
- Publication number 20080305613
- Publication date Dec 11, 2008
- Advanced Micro Devices, Inc.
- Mario M. PELELLA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE ON AN SOI SUBSTRATE
- Publication number 20080124884
- Publication date May 29, 2008
- Mario M. Pelella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit and method of manufacture
- Publication number 20060246707
- Publication date Nov 2, 2006
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTABLE OPEN CIRCUIT AND ANTI-FUSE ELEMENT
- Publication number 20060208321
- Publication date Sep 21, 2006
- Advanced Micro Devices, Inc.
- Darin A. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor component and method of manufacture
- Publication number 20060197154
- Publication date Sep 7, 2006
- Advanced Micro Devices, Inc.
- Mario M. Pelella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming planarized shallow trench isolation
- Publication number 20050158963
- Publication date Jul 21, 2005
- Advanced Micro Devices, Inc.
- Darin Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing pattern deformation and photoresist poisoning i...
- Publication number 20040023475
- Publication date Feb 5, 2004
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS

Darin A. Chan

Person

Patents Grantslast 30 patents

High-voltage devices integrated on semiconductor-on-insulator subst...

Density-controllable dummy fill strategy for near-MRAM periphery an...

Magnetism-controllable dummy structures in memory device

Body tie test structure for accurate body effect measurement

Body tie test structure for accurate body effect measurement

Process for design of semiconductor circuits

Disposable spacer process for field effect transistor fabrication

Methods for fabricating a semiconductor device on an SOI substrate

Integrated circuit and method of manufacture

Selectable open circuit and anti-fuse element

Semiconductor component and method of manufacture

Conversion of transition metal to silicide through back end process...

Trenches to reduce lateral silicide growth in integrated circuit te...

Selectable open circuit and anti-fuse element, and fabrication meth...

Method for patterning narrow gate lines

Nitride offset spacer to minimize silicon recess by using poly reox...

SOI device with different silicon thicknesses

Method for reducing gate line deformation and reducing gate line wi...

Method for reducing pattern deformation and photoresist poisoning i...

Method for fabricating a semiconductor device using amorphous carbo...

SOI device with wrap-around contact to underside of body, and metho...

Method for shallow trench isolation with removal of strained island...

SOI device with wrap-around contact to underside of body, and metho...

Method of manufacturing semiconductor devices with trench isolation

Methods and arrangements for insulating local interconnects for imp...

Formation of a barrier layer for tungsten damascene interconnects b...

Elimination of residual materials in a multiple-layer interconnect...

Method of fabricating an integrated circuit including a tri-layer p...

Local interconnects for improved alignment tolerance and size reduc...

Multipurpose cap layer dielectric

Patents Applicationslast 30 patents

HIGH-VOLTAGE DEVICES INTEGRATED ON SEMICONDUCTOR-ON-INSULATOR SUBST...

DENSITY-CONTROLLABLE DUMMY FILL STRATEGY FOR NEAR-MRAM PERIPHERY AN...

MAGNETISM-CONTROLLABLE DUMMY STRUCTURES IN MEMORY DEVICE

BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT

PROCESS FOR DESIGN OF SEMICONDUCTOR CIRCUITS

BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT

METHOD FOR FABRICATING AN SOI DEFINED SEMICONDUCTOR DEVICE

METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE ON AN SOI SUBSTRATE

Integrated circuit and method of manufacture

SELECTABLE OPEN CIRCUIT AND ANTI-FUSE ELEMENT

Semiconductor component and method of manufacture

Method of forming planarized shallow trench isolation

Method for reducing pattern deformation and photoresist poisoning i...