David B. Glasco

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Parallel processing system runtime state reload
- Patent number 12,169,443
- Issue date Dec 17, 2024
- Tesla, Inc.
- Daniel William Bailey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous driving controller parallel processor boot order
- Patent number 11,960,901
- Issue date Apr 16, 2024
- Tesla, Inc.
- Patryk Kaminski
- B60 - VEHICLES IN GENERAL
Information Patent Grant
QoS manager for system on a chip communications
- Patent number 11,665,108
- Issue date May 30, 2023
- Tesla, Inc.
- David Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous driving controller encrypted communications
- Patent number 11,646,868
- Issue date May 9, 2023
- Tesla, Inc.
- Thaddeus Fortenberry
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Autonomous driving system component fault prediction
- Patent number 11,640,733
- Issue date May 2, 2023
- Tesla, Inc.
- Atchyuth Gorti
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Autonomous driving controller parallel processor boot order
- Patent number 11,593,119
- Issue date Feb 28, 2023
- Tesla, Inc.
- Patryk Kaminski
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Parallel processing system runtime state reload
- Patent number 11,526,409
- Issue date Dec 13, 2022
- Tesla, Inc.
- Daniel William Bailey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolation of subsystems on a system on a chip
- Patent number 11,423,178
- Issue date Aug 23, 2022
- Tesla, Inc.
- David Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QOS manager for system on a chip communications
- Patent number 11,196,678
- Issue date Dec 7, 2021
- Tesla, Inc.
- David Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous driving controller encrypted communications
- Patent number 11,005,649
- Issue date May 11, 2021
- Tesla, Inc.
- Thaddeus Fortenberry
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Parallel processing system runtime state reload
- Patent number 10,802,929
- Issue date Oct 13, 2020
- Tesla, Inc.
- Daniel William Bailey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status bit cache and backing store
- Patent number 10,515,011
- Issue date Dec 24, 2019
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple protocol engine transaction processing
- Patent number 10,042,804
- Issue date Aug 7, 2018
- Sanmina Corporation
- Charles Edward Watson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mitigating main crossbar load using dedicated connections for certa...
- Patent number 9,367,487
- Issue date Jun 14, 2016
- NVIDIA Corporation
- Dane Mrazek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for tracking accesses to virtual addresses in gra...
- Patent number 9,153,211
- Issue date Oct 6, 2015
- NVIDIA Corporation
- James L. Deming
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Consolidated crossbar that supports a multitude of traffic types
- Patent number 9,098,383
- Issue date Aug 4, 2015
- NVIDIA Corporation
- Sean J. Treichler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for evicting dirty data from a cache using a notificatio...
- Patent number 8,949,541
- Issue date Feb 3, 2015
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction processing using multiple protocol engines
- Patent number 8,898,254
- Issue date Nov 25, 2014
- Charles Edward Watson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Padding buffer requests to avoid reads of invalid data
- Patent number 8,874,844
- Issue date Oct 28, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-class data cache policies
- Patent number 8,868,838
- Issue date Oct 21, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status caching
- Patent number 8,862,823
- Issue date Oct 14, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for maintaining cache coherency across a serial i...
- Patent number 8,782,349
- Issue date Jul 15, 2014
- NVIDIA Corporation
- Brian Keith Langendorf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access management block bind system and method
- Patent number 8,706,975
- Issue date Apr 22, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access techniques utilizing a set-associative translation lo...
- Patent number 8,707,011
- Issue date Apr 22, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access techniques providing for override of a page table
- Patent number 8,700,883
- Issue date Apr 15, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status bit cache and backing store
- Patent number 8,700,862
- Issue date Apr 15, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient line and page organization for compression status bit cac...
- Patent number 8,627,041
- Issue date Jan 7, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for independent invalidation on a per engine basis
- Patent number 8,607,008
- Issue date Dec 10, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrently managing memory access requests
- Patent number 8,601,235
- Issue date Dec 3, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status bit cache with deterministic isochronous latency
- Patent number 8,595,437
- Issue date Nov 26, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTONOMOUS DRIVING CONTROLLER PARALLEL PROCESSOR BOOT ORDER
- Publication number 20230281017
- Publication date Sep 7, 2023
- Tesla, Inc.
- Patryk Kaminski
- B60 - VEHICLES IN GENERAL
Information Patent Application
AUTONOMOUS DRIVING SYSTEM COMPONENT FAULT PREDICTION
- Publication number 20230274591
- Publication date Aug 31, 2023
- Tesla, Inc.
- Atchyuth Gorti
- B60 - VEHICLES IN GENERAL
Information Patent Application
PARALLEL PROCESSING SYSTEM RUNTIME STATE RELOAD
- Publication number 20230102197
- Publication date Mar 30, 2023
- Tesla, Inc.
- Daniel William Bailey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QOS MANAGER FOR SYSTEM ON A CHIP COMMUNICATIONS
- Publication number 20220166726
- Publication date May 26, 2022
- Tesla, Inc.
- David Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS DRIVING CONTROLLER ENCRYPTED COMMUNICATIONS
- Publication number 20210385073
- Publication date Dec 9, 2021
- Tesla, Inc.
- Thaddeus Fortenberry
- B60 - VEHICLES IN GENERAL
Information Patent Application
PARALLEL PROCESSING SYSTEM RUNTIME STATE RELOAD
- Publication number 20210263811
- Publication date Aug 26, 2021
- Tesla, Inc.
- Daniel William Bailey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QOS MANAGER FOR SYSTEM ON A CHIP COMMUNICATIONS
- Publication number 20210126874
- Publication date Apr 29, 2021
- Tesla, Inc.
- David Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS DRIVING SYSTEM COMPONENT FAULT PREDICTION
- Publication number 20200320807
- Publication date Oct 8, 2020
- Tesla, Inc.
- Atchyuth Gorti
- B60 - VEHICLES IN GENERAL
Information Patent Application
AUTONOMOUS DRIVING CONTROLLER ENCRYPTED COMMUNICATIONS
- Publication number 20190334706
- Publication date Oct 31, 2019
- Tesla, Inc.
- Thaddeus Fortenberry
- B60 - VEHICLES IN GENERAL
Information Patent Application
AUTONOMOUS DRIVING CONTROLLER PARALLEL PROCESSOR BOOT ORDER
- Publication number 20190332390
- Publication date Oct 31, 2019
- Tesla, Inc.
- Patryk Kaminski
- B60 - VEHICLES IN GENERAL
Information Patent Application
ISOLATION OF SUBSYSTEMS ON A SYSTEM ON A CHIP
- Publication number 20190332816
- Publication date Oct 31, 2019
- Tesla, Inc.
- David Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL PROCESSING SYSTEM RUNTIME STATE RELOAD
- Publication number 20190205218
- Publication date Jul 4, 2019
- Tesla, Inc.
- Daniel William Bailey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Protocol Engine Transaction Processing
- Publication number 20150074325
- Publication date Mar 12, 2015
- Memory Integrity, LLC
- Charles Edward Watson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION STATUS BIT CACHE AND BACKING STORE
- Publication number 20140237189
- Publication date Aug 21, 2014
- NVIDIA Corporation
- David B. GLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OVERRIDE SYSTEM AND METHOD FOR MEMORY ACCESS MANAGEMENT
- Publication number 20140164716
- Publication date Jun 12, 2014
- David B. GLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTION PROCESSING USING MULTIPLE PROTOCOL ENGINES
- Publication number 20140013079
- Publication date Jan 9, 2014
- Memory Integrity, LLC
- Charles Edward Watson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Class Dependent Clean and Dirty Policy
- Publication number 20130124802
- Publication date May 16, 2013
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MAINTAINING CACHE COHERENCY ACROSS A SERIAL I...
- Publication number 20120290796
- Publication date Nov 15, 2012
- Brian Keith Langendorf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTION PROCESSING MULTIPLE PROTOCOL ENGINES IN SYSTEMS HAVING...
- Publication number 20120089787
- Publication date Apr 12, 2012
- Charles Edward Watson, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CAC...
- Publication number 20110087840
- Publication date Apr 14, 2011
- David B. GLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER
- Publication number 20110072177
- Publication date Mar 24, 2011
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deadlock Avoidance By Marking CPU Traffic As Special
- Publication number 20100153658
- Publication date Jun 17, 2010
- Samuel H. Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System And Method For Maintaining Cache Coherency Across A Serial I...
- Publication number 20100146218
- Publication date Jun 10, 2010
- Brian Keith Langendorf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compression Status Bit Cache And Backing Store
- Publication number 20100138614
- Publication date Jun 3, 2010
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CONCURRENTLY MANAGING MEMORY ACCESS REQUESTS
- Publication number 20100106921
- Publication date Apr 29, 2010
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, and Method For Using Page Table Entries in a Gra...
- Publication number 20090244074
- Publication date Oct 1, 2009
- John S. Montrym
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory access techniques providing for override of page table attri...
- Publication number 20070126756
- Publication date Jun 7, 2007
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing probe traffic in multiprocessor systems
- Publication number 20070055826
- Publication date Mar 8, 2007
- Newisys, Inc., A Delaware corporation
- Eric Morton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing sparse directory evictions in multiprocessor systems via m...
- Publication number 20050251626
- Publication date Nov 10, 2005
- Newisys, Inc.
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communication between and within multi-processor clusters of multi-...
- Publication number 20050034033
- Publication date Feb 10, 2005
- Newisys, Inc.
- Shashank Nemawarkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

David B. Glasco

Person

Patents Grantslast 30 patents

Parallel processing system runtime state reload

Autonomous driving controller parallel processor boot order

QoS manager for system on a chip communications

Autonomous driving controller encrypted communications

Autonomous driving system component fault prediction

Autonomous driving controller parallel processor boot order

Parallel processing system runtime state reload

Isolation of subsystems on a system on a chip

QOS manager for system on a chip communications

Autonomous driving controller encrypted communications

Parallel processing system runtime state reload

Compression status bit cache and backing store

Multiple protocol engine transaction processing

Mitigating main crossbar load using dedicated connections for certa...

Method and system for tracking accesses to virtual addresses in gra...

Consolidated crossbar that supports a multitude of traffic types

Techniques for evicting dirty data from a cache using a notificatio...

Transaction processing using multiple protocol engines

Padding buffer requests to avoid reads of invalid data

Multi-class data cache policies

Compression status caching

System and method for maintaining cache coherency across a serial i...

Memory access management block bind system and method

Memory access techniques utilizing a set-associative translation lo...

Memory access techniques providing for override of a page table

Compression status bit cache and backing store

Efficient line and page organization for compression status bit cac...

System and method for independent invalidation on a per engine basis

System and method for concurrently managing memory access requests

Compression status bit cache with deterministic isochronous latency

Patents Applicationslast 30 patents

AUTONOMOUS DRIVING CONTROLLER PARALLEL PROCESSOR BOOT ORDER

AUTONOMOUS DRIVING SYSTEM COMPONENT FAULT PREDICTION

PARALLEL PROCESSING SYSTEM RUNTIME STATE RELOAD

QOS MANAGER FOR SYSTEM ON A CHIP COMMUNICATIONS

AUTONOMOUS DRIVING CONTROLLER ENCRYPTED COMMUNICATIONS

PARALLEL PROCESSING SYSTEM RUNTIME STATE RELOAD

QOS MANAGER FOR SYSTEM ON A CHIP COMMUNICATIONS

AUTONOMOUS DRIVING SYSTEM COMPONENT FAULT PREDICTION

AUTONOMOUS DRIVING CONTROLLER ENCRYPTED COMMUNICATIONS

AUTONOMOUS DRIVING CONTROLLER PARALLEL PROCESSOR BOOT ORDER

ISOLATION OF SUBSYSTEMS ON A SYSTEM ON A CHIP

PARALLEL PROCESSING SYSTEM RUNTIME STATE RELOAD

Multiple Protocol Engine Transaction Processing

COMPRESSION STATUS BIT CACHE AND BACKING STORE

OVERRIDE SYSTEM AND METHOD FOR MEMORY ACCESS MANAGEMENT

TRANSACTION PROCESSING USING MULTIPLE PROTOCOL ENGINES

Class Dependent Clean and Dirty Policy

SYSTEM AND METHOD FOR MAINTAINING CACHE COHERENCY ACROSS A SERIAL I...

TRANSACTION PROCESSING MULTIPLE PROTOCOL ENGINES IN SYSTEMS HAVING...

EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CAC...

VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER

Deadlock Avoidance By Marking CPU Traffic As Special

System And Method For Maintaining Cache Coherency Across A Serial I...

Compression Status Bit Cache And Backing Store

SYSTEM AND METHOD FOR CONCURRENTLY MANAGING MEMORY ACCESS REQUESTS

Apparatus, System, and Method For Using Page Table Entries in a Gra...

Memory access techniques providing for override of page table attri...

Reducing probe traffic in multiprocessor systems

Managing sparse directory evictions in multiprocessor systems via m...

Communication between and within multi-processor clusters of multi-...