David D. Siek

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of stress-testing an isolation gate in a dynamic random acce...
- Patent number 7,180,802
- Issue date Feb 20, 2007
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of stress-testing an isolation gate in a dynamic random acce...
- Patent number 6,999,362
- Issue date Feb 14, 2006
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing integrated circuit devices
- Patent number 6,930,503
- Issue date Aug 16, 2005
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM array and computer system
- Patent number 6,870,750
- Issue date Mar 22, 2005
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing integrated circuit devices
- Patent number 6,756,805
- Issue date Jun 29, 2004
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
6F2 DRAM array with apparatus for stress testing an isolation gate...
- Patent number 6,735,132
- Issue date May 11, 2004
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
6F2 DRAM array with apparatus for stress testing an isolation gate...
- Patent number 6,590,817
- Issue date Jul 8, 2003
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for detecting or repairing intercell defects in more than on...
- Patent number 6,510,533
- Issue date Jan 21, 2003
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing integrated circuit devices
- Patent number 6,496,027
- Issue date Dec 17, 2002
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for detecting or preparing intercell defects in more than on...
- Patent number 6,167,541
- Issue date Dec 26, 2000
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
Single digit line with cell contact interconnect
- Patent number 6,066,870
- Issue date May 23, 2000
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for hiding data path equilibration time
- Patent number 5,986,955
- Issue date Nov 16, 1999
- Micron Technology , Inc.
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Grant
Single digit line with cell contact interconnect
- Patent number 5,866,928
- Issue date Feb 2, 1999
- Micron Technology, Inc.
- David D. Siek
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
System for testing integrated circuit devices
- Publication number 20050270058
- Publication date Dec 8, 2005
- Micron Technology, Inc.
- Joseph C. Sher
- G01 - MEASURING TESTING
Information Patent Application
Method of stress-testing an isolation gate in a dynamic random acce...
- Publication number 20050236657
- Publication date Oct 27, 2005
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Application
Method of manufacturing a DRAM array
- Publication number 20050057959
- Publication date Mar 17, 2005
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM array, method of manufacturing a DRAM array, and computer system
- Publication number 20040201054
- Publication date Oct 14, 2004
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing integrated circuit devices
- Publication number 20040201399
- Publication date Oct 14, 2004
- Micron Technology, Inc.
- Joseph C. Sher
- G01 - MEASURING TESTING
Information Patent Application
6F2 DRAM array with apparatus for stress testing an isolation gate...
- Publication number 20030198111
- Publication date Oct 23, 2003
- David D. Siek
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing integrated circuit devices
- Publication number 20030090285
- Publication date May 15, 2003
- Micron Technology, Inc.
- Joseph C. Sher
- G01 - MEASURING TESTING
Information Patent Application
6F2 DRAM ARRAY WITH APPARATUS FOR STRESS TESTING AN ISOLATION GATE...
- Publication number 20030016577
- Publication date Jan 23, 2003
- David D. Siek
- H01 - BASIC ELECTRIC ELEMENTS

David D. Siek

Person

Patents Grantslast 30 patents

Method of stress-testing an isolation gate in a dynamic random acce...

Method of stress-testing an isolation gate in a dynamic random acce...

System for testing integrated circuit devices

DRAM array and computer system

System for testing integrated circuit devices

6F2 DRAM array with apparatus for stress testing an isolation gate...

6F2 DRAM array with apparatus for stress testing an isolation gate...

Method for detecting or repairing intercell defects in more than on...

System for testing integrated circuit devices

Method for detecting or preparing intercell defects in more than on...

Single digit line with cell contact interconnect

Method and apparatus for hiding data path equilibration time

Single digit line with cell contact interconnect

Patents Applicationslast 30 patents

System for testing integrated circuit devices

Method of stress-testing an isolation gate in a dynamic random acce...

Method of manufacturing a DRAM array

DRAM array, method of manufacturing a DRAM array, and computer system

System for testing integrated circuit devices

6F2 DRAM array with apparatus for stress testing an isolation gate...

System for testing integrated circuit devices

6F2 DRAM ARRAY WITH APPARATUS FOR STRESS TESTING AN ISOLATION GATE...