David E. Fulkerson

Person

Chanhassen, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and systems for hardening a clocked latch against single ev...
- Patent number 7,411,411
- Issue date Aug 12, 2008
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundancy circuits hardened against single event upsets
- Patent number 7,236,001
- Issue date Jun 26, 2007
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for using layout regions to predict single-event effects
- Patent number 7,236,919
- Issue date Jun 26, 2007
- Honeywell International Inc.
- David E. Fulkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power pulse signaling
- Patent number 7,187,710
- Issue date Mar 6, 2007
- David E. Fulkerson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
SEU hard majority voter for triple redundancy
- Patent number 6,906,388
- Issue date Jun 14, 2005
- Honeywell International, Inc.
- David E. Fulkerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Cold spare circuit for CMOS output circuit
- Patent number 6,794,925
- Issue date Sep 21, 2004
- Honeywell International, Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive threshold voltage control with positive body bias for N an...
- Patent number 6,731,157
- Issue date May 4, 2004
- Honeywell International Inc.
- David E. Fulkerson
- G05 - CONTROLLING REGULATING
Information Patent Grant
SEU hard majority voter for triple redundancy
- Patent number 6,667,520
- Issue date Dec 23, 2003
- Honeywell International Inc.
- David E. Fulkerson
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed output buffers using voltage followers
- Patent number 6,646,470
- Issue date Nov 11, 2003
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS ECL output buffer
- Patent number 6,563,342
- Issue date May 13, 2003
- Honeywell International, Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop with transmission gate in master latch
- Patent number 6,563,356
- Issue date May 13, 2003
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS ECL input buffer
- Patent number 6,535,017
- Issue date Mar 18, 2003
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed output buffers using voltage followers
- Patent number 6,469,543
- Issue date Oct 22, 2002
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Domino logic family
- Patent number 6,362,659
- Issue date Mar 26, 2002
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed logic family
- Patent number 6,252,426
- Issue date Jun 26, 2001
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Boxes for Soft Error Rate Calculation
- Publication number 20070166847
- Publication date Jul 19, 2007
- Honeywell International Inc.
- David E. Fulkerson
- G01 - MEASURING TESTING
Information Patent Application
Redundancy circuits hardened against single event upsets
- Publication number 20070052442
- Publication date Mar 8, 2007
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for using layout regions to predict single-event effects
- Publication number 20070033559
- Publication date Feb 8, 2007
- Honeywell International Inc.
- David E. Fulkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Single-event-effect hardened circuitry
- Publication number 20060267653
- Publication date Nov 30, 2006
- Honeywell International Inc.
- David Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEU hard majority voter for triple redundancy
- Publication number 20040099913
- Publication date May 27, 2004
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adaptive threshold voltage control with positive body bias for N an...
- Publication number 20030132735
- Publication date Jul 17, 2003
- David E. Fulkerson
- G05 - CONTROLLING REGULATING
Information Patent Application
High speed output buffers using voltage followers
- Publication number 20020180482
- Publication date Dec 5, 2002
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Flip-flop with transmission gate in master latch
- Publication number 20020093368
- Publication date Jul 18, 2002
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH SPEED LATCH AND FLIP-FLOP
- Publication number 20010050583
- Publication date Dec 13, 2001
- DAVID E. FULKERSON
- H03 - BASIC ELECTRONIC CIRCUITRY

David E. Fulkerson

Person

Patents Grantslast 30 patents

Methods and systems for hardening a clocked latch against single ev...

Redundancy circuits hardened against single event upsets

Method for using layout regions to predict single-event effects

Low power pulse signaling

SEU hard majority voter for triple redundancy

Cold spare circuit for CMOS output circuit

Adaptive threshold voltage control with positive body bias for N an...

SEU hard majority voter for triple redundancy

High speed output buffers using voltage followers

CMOS ECL output buffer

Flip-flop with transmission gate in master latch

CMOS ECL input buffer

High speed output buffers using voltage followers

Domino logic family

High speed logic family

Patents Applicationslast 30 patents

Boxes for Soft Error Rate Calculation

Redundancy circuits hardened against single event upsets

Method for using layout regions to predict single-event effects

Single-event-effect hardened circuitry

SEU hard majority voter for triple redundancy

Adaptive threshold voltage control with positive body bias for N an...

High speed output buffers using voltage followers

Flip-flop with transmission gate in master latch

HIGH SPEED LATCH AND FLIP-FLOP