David Keppel

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable address range engine for larger region sizes
- Patent number 11,989,135
- Issue date May 21, 2024
- Intel Corporation
- Farah E. Fargo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Valid bits of a translation lookaside buffer (TLB) for checking mul...
- Patent number 11,055,232
- Issue date Jul 6, 2021
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance monitoring
- Patent number 10,771,404
- Issue date Sep 8, 2020
- Intel Corporation
- David Keppel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for efficiently implementing a processor pipeline
- Patent number 10,409,763
- Issue date Sep 10, 2019
- Intel Corporation
- Patrick P. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric addressing
- Patent number 10,331,550
- Issue date Jun 25, 2019
- Intel Corporation
- David Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabric-integrated data pulling engine
- Patent number 10,200,310
- Issue date Feb 5, 2019
- Intel Corporation
- James Dinan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for aggregation-based message synchronization
- Patent number 10,178,041
- Issue date Jan 8, 2019
- Intel Corporation
- James Dinan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Controlling processor consumption using on-off keying having a maxi...
- Patent number 10,168,765
- Issue date Jan 1, 2019
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for performance inspection at an endpoint node
- Patent number 10,135,708
- Issue date Nov 20, 2018
- Intel Corporation
- James Dinan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for sideband performance tracing of network traffic
- Patent number 10,135,711
- Issue date Nov 20, 2018
- Intel Corporation
- Robert C. Zak
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Opportunistic power management for managing intermittent power avai...
- Patent number 10,061,376
- Issue date Aug 28, 2018
- Intel Corporation
- Helia Naeimi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for bulk register reclamation
- Patent number 10,061,587
- Issue date Aug 28, 2018
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for support of code modification
- Patent number 9,971,599
- Issue date May 15, 2018
- Intel Corporation
- John H. Kelm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for flushing dirty cache lines based on cache...
- Patent number 9,965,023
- Issue date May 8, 2018
- Intel Corporation
- David Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling power consumption of a processor using interrupt-mediat...
- Patent number 9,766,685
- Issue date Sep 19, 2017
- Intel Corporation
- David Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for support of code modification
- Patent number 9,652,268
- Issue date May 16, 2017
- Intel Corporation
- John H. Kelm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Collective communications apparatus and method for parallel systems
- Patent number 9,477,628
- Issue date Oct 25, 2016
- Intel Corporation
- Allan D. Knies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for reduced core entry into a power state havi...
- Patent number 9,442,849
- Issue date Sep 13, 2016
- Intel Corporation
- David Keppel
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Controlling processor consumption using on-off keying having a maxi...
- Patent number 9,354,694
- Issue date May 31, 2016
- Intel Corporation
- David Pardo Keppel
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for managing a spin transfer torque memory
- Patent number 9,342,403
- Issue date May 17, 2016
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block-level sleep logic
- Patent number 9,329,658
- Issue date May 3, 2016
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling of binary translated self modifying code and cross modifyi...
- Patent number 9,116,729
- Issue date Aug 25, 2015
- Intel Corporation
- Nirajan L. Cooray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for integration of interpretation and translation in a micro...
- Patent number 8,418,153
- Issue date Apr 9, 2013
- Robert Bedichek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for switching between interpretation and dynamic translation...
- Patent number 7,761,857
- Issue date Jul 20, 2010
- Robert Bedichek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling nested faults
- Patent number 7,640,450
- Issue date Dec 29, 2009
- H. Peter Anvin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interpage prologue to protect virtual address mappings
- Patent number 7,617,088
- Issue date Nov 10, 2009
- Robert Bedichek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interpage prologue to protect virtual address mappings
- Patent number 6,845,353
- Issue date Jan 18, 2005
- Transmeta Corporation
- Robert Bedichek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling nested faults
- Patent number 6,829,719
- Issue date Dec 7, 2004
- Transmeta Corporation
- H. Peter Anvin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of enable bits to control execution of selected instructions
- Patent number 6,738,892
- Issue date May 18, 2004
- Transmeta Corporation
- Brett Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for using rate of exception event generation during executio...
- Patent number 6,714,904
- Issue date Mar 30, 2004
- Transmeta Corporation
- Linus Torvalds
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Apparatuses, Devices, Methods and Computer Programs for Allocating...
- Publication number 20240126680
- Publication date Apr 18, 2024
- David KEPPEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A Concept for Writing Data to a Limited-Size Data Buffer
- Publication number 20240126440
- Publication date Apr 18, 2024
- Lawrence STEWART
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED TRANSLATION LOOKASIDE BUFFER SET REBALANCING
- Publication number 20220206955
- Publication date Jun 30, 2022
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METADATA COMPACTION IN PACKET COALESCING
- Publication number 20220201103
- Publication date Jun 23, 2022
- Intel Corporation
- David KEPPEL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CACHE PROBE TRANSACTION FILTERING
- Publication number 20220107897
- Publication date Apr 7, 2022
- Intel Corporation
- David KEPPEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED NETWORK LOAD WITH COMBINED PUT OR GET AND RECEIVER-MANAGED...
- Publication number 20220011966
- Publication date Jan 13, 2022
- Intel Corporation
- David KEPPEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE ADDRESS RANGE ENGINE FOR LARGER REGION SIZES
- Publication number 20200233814
- Publication date Jul 23, 2020
- Intel Corporation
- Farah E. FARGO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALID BITS OF A TRANSLATION LOOKASIDE BUFFER (TLB) FOR CHECKING MUL...
- Publication number 20190227947
- Publication date Jul 25, 2019
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYMMETRIC ADDRESSING
- Publication number 20180217925
- Publication date Aug 2, 2018
- Intel Corporation
- David Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE MONITORING
- Publication number 20180183732
- Publication date Jun 28, 2018
- Intel Corporation
- David Keppel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR DYNAMIC WORK QUEUE MANAGEMENT
- Publication number 20170289242
- Publication date Oct 5, 2017
- David Keppel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Instruction and Logic for Support of Code Modification
- Publication number 20170242705
- Publication date Aug 24, 2017
- Intel Corporation
- John H. Kelm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FABRIC-INTEGRATED DATA PULLING ENGINE
- Publication number 20170185561
- Publication date Jun 29, 2017
- Intel Corporation
- James Dinan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technologies for inline network traffic performance tracing
- Publication number 20170187587
- Publication date Jun 29, 2017
- David Keppel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR SIDEBAND PERFORMANCE TRACING OF NETWORK TRAFFIC
- Publication number 20170180235
- Publication date Jun 22, 2017
- Robert C. Zak
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR PERFORMANCE INSPECTION AT AN ENDPOINT NODE
- Publication number 20170093670
- Publication date Mar 30, 2017
- Intel Corporation
- James Dinan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR AGGREGATION-BASED MESSAGE SYNCHRONIZATION
- Publication number 20170085442
- Publication date Mar 23, 2017
- Intel Corporation
- James Dinan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS AND METHOD FOR REDUCED CORE ENTRY INTO A POWER STATE HAVI...
- Publication number 20170003734
- Publication date Jan 5, 2017
- Intel Corporation
- DAVID KEPPEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPPORTUNISTIC POWER MANAGEMENT FOR MANAGING INTERMITTENT POWER AVAI...
- Publication number 20160378169
- Publication date Dec 29, 2016
- Intel Corporation
- HELIA NAEIMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING PROCESSOR CONSUMPTION USING ON-OFF KEYING HAVING A MAXI...
- Publication number 20160320832
- Publication date Nov 3, 2016
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION
- Publication number 20160283247
- Publication date Sep 29, 2016
- Intel Corporation
- Girish Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR PAGE TABLE WALK CHANGE-BITS
- Publication number 20160179662
- Publication date Jun 23, 2016
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION
- Publication number 20160092222
- Publication date Mar 31, 2016
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE
- Publication number 20150378731
- Publication date Dec 31, 2015
- PATRICK P. LAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Support of Code Modification
- Publication number 20150277915
- Publication date Oct 1, 2015
- John H. Kelm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MANAGING A SPIN TRANSFER TORQUE MEMORY
- Publication number 20150278011
- Publication date Oct 1, 2015
- Intel Corporation
- DAVID PARDO KEPPEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COLLECTIVE COMMUNICATIONS APPARATUS AND METHOD FOR PARALLEL SYSTEMS
- Publication number 20150095542
- Publication date Apr 2, 2015
- Allan D. Knies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Power Consumption Of A Processor Using Interrupt-Mediat...
- Publication number 20140344596
- Publication date Nov 20, 2014
- David Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Processor Consumption Using On-Off Keying Having A Maxi...
- Publication number 20140281602
- Publication date Sep 18, 2014
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYI...
- Publication number 20140189659
- Publication date Jul 3, 2014
- Nirajan L. Cooray
- G06 - COMPUTING CALCULATING COUNTING

David Keppel

Person

Patents Grantslast 30 patents

Programmable address range engine for larger region sizes

Valid bits of a translation lookaside buffer (TLB) for checking mul...

Performance monitoring

Apparatus and method for efficiently implementing a processor pipeline

Symmetric addressing

Fabric-integrated data pulling engine

Technologies for aggregation-based message synchronization

Controlling processor consumption using on-off keying having a maxi...

Technologies for performance inspection at an endpoint node

Technologies for sideband performance tracing of network traffic

Opportunistic power management for managing intermittent power avai...

Instruction and logic for bulk register reclamation

Instruction and logic for support of code modification

Apparatus and method for flushing dirty cache lines based on cache...

Controlling power consumption of a processor using interrupt-mediat...

Instruction and logic for support of code modification

Collective communications apparatus and method for parallel systems

Apparatus and method for reduced core entry into a power state havi...

Controlling processor consumption using on-off keying having a maxi...

Method and apparatus for managing a spin transfer torque memory

Block-level sleep logic

Handling of binary translated self modifying code and cross modifyi...

Method for integration of interpretation and translation in a micro...

Method for switching between interpretation and dynamic translation...

Method and apparatus for handling nested faults

Interpage prologue to protect virtual address mappings

Interpage prologue to protect virtual address mappings

Method and apparatus for handling nested faults

Use of enable bits to control execution of selected instructions

System for using rate of exception event generation during executio...

Patents Applicationslast 30 patents

Apparatuses, Devices, Methods and Computer Programs for Allocating...

A Concept for Writing Data to a Limited-Size Data Buffer

AUTOMATED TRANSLATION LOOKASIDE BUFFER SET REBALANCING

METADATA COMPACTION IN PACKET COALESCING

CACHE PROBE TRANSACTION FILTERING

REDUCED NETWORK LOAD WITH COMBINED PUT OR GET AND RECEIVER-MANAGED...

PROGRAMMABLE ADDRESS RANGE ENGINE FOR LARGER REGION SIZES

VALID BITS OF A TRANSLATION LOOKASIDE BUFFER (TLB) FOR CHECKING MUL...

SYMMETRIC ADDRESSING

PERFORMANCE MONITORING

TECHNOLOGIES FOR DYNAMIC WORK QUEUE MANAGEMENT

Instruction and Logic for Support of Code Modification

FABRIC-INTEGRATED DATA PULLING ENGINE

Technologies for inline network traffic performance tracing

TECHNOLOGIES FOR SIDEBAND PERFORMANCE TRACING OF NETWORK TRAFFIC

TECHNOLOGIES FOR PERFORMANCE INSPECTION AT AN ENDPOINT NODE

TECHNOLOGIES FOR AGGREGATION-BASED MESSAGE SYNCHRONIZATION

APPARATUS AND METHOD FOR REDUCED CORE ENTRY INTO A POWER STATE HAVI...

OPPORTUNISTIC POWER MANAGEMENT FOR MANAGING INTERMITTENT POWER AVAI...

CONTROLLING PROCESSOR CONSUMPTION USING ON-OFF KEYING HAVING A MAXI...

APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION

INSTRUCTION AND LOGIC FOR PAGE TABLE WALK CHANGE-BITS

INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION

APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE

Instruction and Logic for Support of Code Modification

METHOD AND APPARATUS FOR MANAGING A SPIN TRANSFER TORQUE MEMORY

COLLECTIVE COMMUNICATIONS APPARATUS AND METHOD FOR PARALLEL SYSTEMS

Controlling Power Consumption Of A Processor Using Interrupt-Mediat...

Controlling Processor Consumption Using On-Off Keying Having A Maxi...

HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYI...