David L. Hill

Person

Cornellus, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Communicating via an in-die interconnect
- Patent number 8,205,111
- Issue date Jun 19, 2012
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualization of pin functionality in a point-to-point interface
- Patent number 7,783,809
- Issue date Aug 24, 2010
- Intel Corporation
- Keshavan K. Tiruvallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 7,487,305
- Issue date Feb 3, 2009
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for suspending execution of a thread until a s...
- Patent number 7,363,474
- Issue date Apr 22, 2008
- Intel Corporation
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic priority external transaction system
- Patent number 7,143,242
- Issue date Nov 28, 2006
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 7,133,981
- Issue date Nov 7, 2006
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherency techniques for suspending execution of a thread until a s...
- Patent number 7,127,561
- Issue date Oct 24, 2006
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to determine the bootstrap processor from a plura...
- Patent number 6,925,556
- Issue date Aug 2, 2005
- Intel Corporation
- David Lawrence Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced highly pipelined bus architecture
- Patent number 6,907,487
- Issue date Jun 14, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop phase in a highly pipelined bus architecture
- Patent number 6,880,031
- Issue date Apr 12, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,807,592
- Issue date Oct 19, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Response and data phases in a highly pipelined bus architecture
- Patent number 6,804,735
- Issue date Oct 12, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 6,782,457
- Issue date Aug 24, 2004
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch queue
- Patent number 6,742,085
- Issue date May 25, 2004
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,735,675
- Issue date May 11, 2004
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External bus transaction scheduling system
- Patent number 6,732,242
- Issue date May 4, 2004
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic priority external transaction system
- Patent number 6,654,837
- Issue date Nov 25, 2003
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,609,171
- Issue date Aug 19, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 6,606,692
- Issue date Aug 12, 2003
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,601,121
- Issue date Jul 29, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,578,114
- Issue date Jun 10, 2003
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch queue
- Patent number 6,557,081
- Issue date Apr 29, 2003
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 6,499,090
- Issue date Dec 24, 2002
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch queue
- Patent number 6,484,239
- Issue date Nov 19, 2002
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,434,677
- Issue date Aug 13, 2002
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction system in a processing agent having minimal delay
- Patent number 6,412,091
- Issue date Jun 25, 2002
- Intel Corporation
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Recycle mechanism for a processing agent
- Patent number 6,401,172
- Issue date Jun 4, 2002
- Intel Corp.
- Chinna Prudvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write-combining device for uncacheable stores
- Patent number 6,334,171
- Issue date Dec 25, 2001
- Intel Corporation
- Dave L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction system in a processing agent having minimal delay
- Patent number 6,269,465
- Issue date Jul 31, 2001
- Intel Corporation
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Prefetch queue responsive to read request sequences
- Patent number 6,216,208
- Issue date Apr 10, 2001
- Intel Corporation
- Robert Greiner
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Communicating Via An In-Die Interconnect
- Publication number 20100174936
- Publication date Jul 8, 2010
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for suspending execution of a thread until a s...
- Publication number 20080034190
- Publication date Feb 7, 2008
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIORITIZED BUS REQUEST SCHEDULING MECHANISM FOR PROCESSING DEVICES
- Publication number 20070094462
- Publication date Apr 26, 2007
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Early global observation point for a uniprocessor system
- Publication number 20070073977
- Publication date Mar 29, 2007
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtualization of pin functionality in a point-to-point interface
- Publication number 20070002760
- Publication date Jan 4, 2007
- Keshavan K. Tiruvallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prioritized bus request scheduling mechanism for processing devices
- Publication number 20050268051
- Publication date Dec 1, 2005
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic priority external transaction system
- Publication number 20040059854
- Publication date Mar 25, 2004
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prioritized bus request scheduling mechanism for processing devices
- Publication number 20030196050
- Publication date Oct 16, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prefetch queue
- Publication number 20030191901
- Publication date Oct 9, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
External bus transaction scheduling system
- Publication number 20030188107
- Publication date Oct 2, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for suspending execution of a thread until a s...
- Publication number 20030126186
- Publication date Jul 3, 2003
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction sequences for suspending execution of a thread until a...
- Publication number 20030126379
- Publication date Jul 3, 2003
- Shiv Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Suspending execution of a thread in a multi-threaded processor
- Publication number 20030126416
- Publication date Jul 3, 2003
- Deborah T. Marr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coherency techniques for suspending execution of a thread until a s...
- Publication number 20030126375
- Publication date Jul 3, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for altering data length to zero to maintain c...
- Publication number 20030110359
- Publication date Jun 12, 2003
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prioritized bus request scheduling mechanism for processing devices
- Publication number 20030018863
- Publication date Jan 23, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prefetch queue
- Publication number 20030009633
- Publication date Jan 9, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for altering data length to zero to maintain c...
- Publication number 20020156982
- Publication date Oct 24, 2002
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Response and data phases in a highly pipelined bus architecture
- Publication number 20020147875
- Publication date Oct 10, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system to determine the bootstrap processor
- Publication number 20020112151
- Publication date Aug 15, 2002
- David Lawrence Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020038397
- Publication date Mar 28, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020029307
- Publication date Mar 7, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced highly pipelined bus architecture
- Publication number 20010037421
- Publication date Nov 1, 2001
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop phase in a highly pipelined bus architecture
- Publication number 20010037424
- Publication date Nov 1, 2001
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error correction system in a processing agent having minimal delay
- Publication number 20010020286
- Publication date Sep 6, 2001
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY

David L. Hill

Person

Patents Grantslast 30 patents

Communicating via an in-die interconnect

Virtualization of pin functionality in a point-to-point interface

Prioritized bus request scheduling mechanism for processing devices

Method and apparatus for suspending execution of a thread until a s...

Dynamic priority external transaction system

Prioritized bus request scheduling mechanism for processing devices

Coherency techniques for suspending execution of a thread until a s...

Method and system to determine the bootstrap processor from a plura...

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Response and data phases in a highly pipelined bus architecture

Prioritized bus request scheduling mechanism for processing devices

Prefetch queue

Method and apparatus for altering data length to zero to maintain c...

External bus transaction scheduling system

Dynamic priority external transaction system

Quad pumped bus architecture and protocol

Prioritized bus request scheduling mechanism for processing devices

Quad pumped bus architecture and protocol

Method and apparatus for altering data length to zero to maintain c...

Prefetch queue

Prioritized bus request scheduling mechanism for processing devices

Prefetch queue

Method and apparatus for altering data length to zero to maintain c...

Error correction system in a processing agent having minimal delay

Recycle mechanism for a processing agent

Write-combining device for uncacheable stores

Error correction system in a processing agent having minimal delay

Prefetch queue responsive to read request sequences

Patents Applicationslast 30 patents

Communicating Via An In-Die Interconnect

Method and apparatus for suspending execution of a thread until a s...

PRIORITIZED BUS REQUEST SCHEDULING MECHANISM FOR PROCESSING DEVICES

Early global observation point for a uniprocessor system

Virtualization of pin functionality in a point-to-point interface

Prioritized bus request scheduling mechanism for processing devices

Dynamic priority external transaction system

Prioritized bus request scheduling mechanism for processing devices

Prefetch queue

External bus transaction scheduling system

Method and apparatus for suspending execution of a thread until a s...

Instruction sequences for suspending execution of a thread until a...

Suspending execution of a thread in a multi-threaded processor

Coherency techniques for suspending execution of a thread until a s...

Method and apparatus for altering data length to zero to maintain c...

Prioritized bus request scheduling mechanism for processing devices

Prefetch queue

Method and apparatus for altering data length to zero to maintain c...

Response and data phases in a highly pipelined bus architecture

Method and system to determine the bootstrap processor

Quad pumped bus architecture and protocol

Quad pumped bus architecture and protocol

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture

Error correction system in a processing agent having minimal delay