David M. Dobuzinsky

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Embedded DRAM memory cell with additional patterning layer for impr...
- Patent number 8,772,850
- Issue date Jul 8, 2014
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded DRAM memory cell with additional patterning layer for impr...
- Patent number 8,426,268
- Issue date Apr 23, 2013
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical SOI trench SONOS cell
- Patent number 8,008,713
- Issue date Aug 30, 2011
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation structure compatible with SOI embedded DRAM
- Patent number 8,003,488
- Issue date Aug 23, 2011
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical SOI trench SONOS cell
- Patent number 7,893,485
- Issue date Feb 22, 2011
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for non-selective shallow trench isolation reactive ion etch...
- Patent number 7,871,893
- Issue date Jan 18, 2011
- International Business Machines Corporation
- Gregory Costrini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly filled substrate contact on SOI structure
- Patent number 7,592,245
- Issue date Sep 22, 2009
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for enhancing trench capacitance and trench capacitor
- Patent number 7,560,360
- Issue date Jul 14, 2009
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical SOI trench SONOS cell
- Patent number 7,514,323
- Issue date Apr 7, 2009
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
STI formation in semiconductor device including SOI and bulk silico...
- Patent number 7,394,131
- Issue date Jul 1, 2008
- International Business Machines Corporation
- Michael D. Steigerwalt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly filled substrate contact on SOI structure
- Patent number 7,358,172
- Issue date Apr 15, 2008
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
STI formation in semiconductor device including SOI and bulk silico...
- Patent number 7,118,986
- Issue date Oct 10, 2006
- International Business Machines Corporation
- Michael D. Steigerwalt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of controlled sublithographic structures
- Patent number 7,087,532
- Issue date Aug 8, 2006
- International Business Machines Corporation
- David M Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI trench capacitor cell incorporating a low-leakage floating body...
- Patent number 6,964,897
- Issue date Nov 15, 2005
- International Business Machines Corporation
- Karen A. Bard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing erosion of a nitride gate cap layer during react...
- Patent number 6,960,523
- Issue date Nov 1, 2005
- Infineon Technolgies AG
- Michael Maldei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced cap layer erosion for borderless contacts
- Patent number 6,890,815
- Issue date May 10, 2005
- Infineon Technologies AG
- Johnathan Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etching openings of different depths using a single mask layer meth...
- Patent number 6,887,785
- Issue date May 3, 2005
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hard mask integrated etch process for patterning of silicon oxide a...
- Patent number 6,869,542
- Issue date Mar 22, 2005
- International Business Machines Corporation
- Sadanand V. Desphande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned borderless contacts
- Patent number 6,809,027
- Issue date Oct 26, 2004
- International Business Machines Corporation
- Jay W. Strane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making self-aligned borderless contacts
- Patent number 6,806,177
- Issue date Oct 19, 2004
- International Business Machines Corporation
- Jay W. Strane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of improving etch uniformity in deep silicon etching
- Patent number 6,806,200
- Issue date Oct 19, 2004
- International Business Machines Corporation
- David Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carbon-graded layer for improved adhesion of low-k dielectrics to s...
- Patent number 6,740,539
- Issue date May 25, 2004
- International Business Machines Corporation
- Richard A. Conti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to enhance epitaxial regrowth in amorphous silicon contacts
- Patent number 6,740,568
- Issue date May 25, 2004
- Infineon Technologies AG
- Yun Yu Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective nitride: oxide anisotropic etch process
- Patent number 6,656,375
- Issue date Dec 2, 2003
- International Business Machines Corporation
- Michael D. Armacost
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carbon-graded layer for improved adhesion of low-k dielectrics to s...
- Patent number 6,570,256
- Issue date May 27, 2003
- International Business Machines Corporation
- Richard A. Conti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual layer hard mask for eDRAM gate etch process
- Patent number 6,518,151
- Issue date Feb 11, 2003
- International Business Machines Corporation
- David Mark Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming wires on an integrated circuit chip
- Patent number 6,268,293
- Issue date Jul 31, 2001
- International Business Machines Corporation
- Lawrence Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resist formulation which minimizes blistering during etching
- Patent number 6,207,353
- Issue date Mar 27, 2001
- International Business Machines Corporation
- Michael D. Armacost
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Integrated circuits having reduced stress in metallization
- Patent number 6,208,008
- Issue date Mar 27, 2001
- International Business Machines Corporation
- Kenneth C. Arndt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of controllably forming a LOCOS oxide layer over a portion o...
- Patent number 6,153,474
- Issue date Nov 28, 2000
- International Business Machines Corporation
- Herbert Lei Ho
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPR...
- Publication number 20130228840
- Publication date Sep 5, 2013
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPR...
- Publication number 20100193852
- Publication date Aug 5, 2010
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL SOI TRENCH SONOS CELL
- Publication number 20090224308
- Publication date Sep 10, 2009
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH...
- Publication number 20090189242
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Gregory Costrini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL SOI TRENCH SONOS CELL
- Publication number 20090158234
- Publication date Jun 18, 2009
- INTERNATIONAL MACHINES BUSINESS CORPORATION
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES
- Publication number 20090104776
- Publication date Apr 23, 2009
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM
- Publication number 20090079027
- Publication date Mar 26, 2009
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR ETCHING METHODS
- Publication number 20090047791
- Publication date Feb 19, 2009
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR
- Publication number 20080248625
- Publication date Oct 9, 2008
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR
- Publication number 20080122030
- Publication date May 29, 2008
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE
- Publication number 20080113507
- Publication date May 15, 2008
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE
- Publication number 20070196963
- Publication date Aug 23, 2007
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL SOI TRENCH SONOS CELL
- Publication number 20070122971
- Publication date May 31, 2007
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICO...
- Publication number 20060244093
- Publication date Nov 2, 2006
- Michael D. Steigerwalt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of Controlled Sublithographic Structures
- Publication number 20060068596
- Publication date Mar 30, 2006
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICO...
- Publication number 20050282392
- Publication date Dec 22, 2005
- International Business Machines Corporation
- Michael D. Steigerwalt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS
- Publication number 20050051839
- Publication date Mar 10, 2005
- Johnathan Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM BURIED STRAP PROCESS WITH SILICON CARBIDE
- Publication number 20050017282
- Publication date Jan 27, 2005
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to improve bitline contact formation using a line mask
- Publication number 20050014332
- Publication date Jan 20, 2005
- Infineon Technologies North America Corp.
- Michael Maldei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI TRENCH CAPACITOR CELL INCORPORATING A LOW-LEAKAGE FLOATING BODY...
- Publication number 20040248363
- Publication date Dec 9, 2004
- International Business Machines Corporation
- Karen A. Bard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of reducing erosion of a nitride gate cap layer during react...
- Publication number 20040195607
- Publication date Oct 7, 2004
- Infineon Technologies North America Corp.
- Michael Maldei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HARD MASK INTEGRATED ETCH PROCESS FOR PATTERNING OF SILICON OXIDE A...
- Publication number 20040178169
- Publication date Sep 16, 2004
- International Business Machines Corporation
- Sadanand V. Desphande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Magnetic mirror for protection of consumable parts during plasma pr...
- Publication number 20040112294
- Publication date Jun 17, 2004
- International Business Machines Corporation
- Scott D. Allen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Magnetic mirror for preventing wafer edge damage during dry etching
- Publication number 20040112544
- Publication date Jun 17, 2004
- Hongwen Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned borderless contacts
- Publication number 20040104409
- Publication date Jun 3, 2004
- International Business Machines Corporation
- Jay W. Strane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of improving etch uniformity in deep silicon etching
- Publication number 20040092122
- Publication date May 13, 2004
- International Business Machines Corporation
- David Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to enhance epi-regrowth in amorphous poly CB contacts
- Publication number 20040018680
- Publication date Jan 29, 2004
- Yun Yu Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned borderless contacts
- Publication number 20030228752
- Publication date Dec 11, 2003
- International Business Machines Corporation
- Jay W. Strane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Carbon-graded layer for improved adhesion of low-k dielectrics to s...
- Publication number 20030153198
- Publication date Aug 14, 2003
- Richard A. Conti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL LAYER HARD MASK FOR EDRAM GATE ETCH PROCESS
- Publication number 20030032269
- Publication date Feb 13, 2003
- International Business Machines Corporation
- David Mark Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS

David M. Dobuzinsky

Person

Patents Grantslast 30 patents

Embedded DRAM memory cell with additional patterning layer for impr...

Embedded DRAM memory cell with additional patterning layer for impr...

Vertical SOI trench SONOS cell

Shallow trench isolation structure compatible with SOI embedded DRAM

Vertical SOI trench SONOS cell

Method for non-selective shallow trench isolation reactive ion etch...

Poly filled substrate contact on SOI structure

Methods for enhancing trench capacitance and trench capacitor

Vertical SOI trench SONOS cell

STI formation in semiconductor device including SOI and bulk silico...

Poly filled substrate contact on SOI structure

STI formation in semiconductor device including SOI and bulk silico...

Formation of controlled sublithographic structures

SOI trench capacitor cell incorporating a low-leakage floating body...

Method of reducing erosion of a nitride gate cap layer during react...

Reduced cap layer erosion for borderless contacts

Etching openings of different depths using a single mask layer meth...

Hard mask integrated etch process for patterning of silicon oxide a...

Self-aligned borderless contacts

Method of making self-aligned borderless contacts

Method of improving etch uniformity in deep silicon etching

Carbon-graded layer for improved adhesion of low-k dielectrics to s...

Method to enhance epitaxial regrowth in amorphous silicon contacts

Selective nitride: oxide anisotropic etch process

Carbon-graded layer for improved adhesion of low-k dielectrics to s...

Dual layer hard mask for eDRAM gate etch process

Method of forming wires on an integrated circuit chip

Resist formulation which minimizes blistering during etching

Integrated circuits having reduced stress in metallization

Method of controllably forming a LOCOS oxide layer over a portion o...

Patents Applicationslast 30 patents

EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPR...

EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPR...

VERTICAL SOI TRENCH SONOS CELL

METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH...

VERTICAL SOI TRENCH SONOS CELL

METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES

SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM

SEMICONDUCTOR ETCHING METHODS

METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR

METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR

POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE

POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE

VERTICAL SOI TRENCH SONOS CELL

STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICO...

Formation of Controlled Sublithographic Structures

STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICO...

REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS

DRAM BURIED STRAP PROCESS WITH SILICON CARBIDE

Method to improve bitline contact formation using a line mask

SOI TRENCH CAPACITOR CELL INCORPORATING A LOW-LEAKAGE FLOATING BODY...

Method of reducing erosion of a nitride gate cap layer during react...

HARD MASK INTEGRATED ETCH PROCESS FOR PATTERNING OF SILICON OXIDE A...

Magnetic mirror for protection of consumable parts during plasma pr...

Magnetic mirror for preventing wafer edge damage during dry etching

Self-aligned borderless contacts

Method of improving etch uniformity in deep silicon etching

Method to enhance epi-regrowth in amorphous poly CB contacts

Self-aligned borderless contacts

Carbon-graded layer for improved adhesion of low-k dielectrics to s...

DUAL LAYER HARD MASK FOR EDRAM GATE ETCH PROCESS