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David P. Chengson
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Aptos, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Electrical signature fault detection
Patent number
11,156,651
Issue date
Oct 26, 2021
Juniper Networks, Inc.
David P. Chengson
G01 - MEASURING TESTING
Information
Patent Grant
Grid array pattern for crosstalk reduction
Patent number
10,455,690
Issue date
Oct 22, 2019
Juniper Networks, Inc.
David P. Chengson
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Grid array pattern for crosstalk reduction
Patent number
10,455,691
Issue date
Oct 22, 2019
Juniper Networks, Inc.
David P. Chengson
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Placement of vias in printed circuit board circuits
Patent number
10,383,213
Issue date
Aug 13, 2019
Juniper Networks, Inc.
David P. Chengson
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Electrical signature fault detection
Patent number
10,365,314
Issue date
Jul 30, 2019
Juniper Networks, Inc.
David P. Chengson
G01 - MEASURING TESTING
Information
Patent Grant
Placement of vias in printed circuit board circuits
Patent number
10,231,325
Issue date
Mar 12, 2019
Juniper Networks, Inc.
David P. Chengson
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Systems and methods for error detection and correction
Patent number
10,069,596
Issue date
Sep 4, 2018
Juniper Networks, Inc.
David P. Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Digital bit insertion for clock recovery
Patent number
9,237,003
Issue date
Jan 12, 2016
Juniper Networks, Inc.
David P. Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Systems and methods for reducing reflections and frequency dependen...
Patent number
8,675,483
Issue date
Mar 18, 2014
Juniper Networks, Inc.
David Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Testing vias formed in printed circuit boards
Patent number
8,508,248
Issue date
Aug 13, 2013
Juniper Networks, Inc.
David P. Chengson
G01 - MEASURING TESTING
Information
Patent Grant
Low latency serial memory interface
Patent number
8,452,908
Issue date
May 28, 2013
Juniper Networks, Inc.
David P. Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Multi-interface compatible bus over a common physical connection
Patent number
8,411,695
Issue date
Apr 2, 2013
Juniper Networks, Inc.
David P. Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Error-free startup of low phase noise oscillators
Patent number
8,164,392
Issue date
Apr 24, 2012
Juniper Networks, Inc.
David P. Chengson
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Source synchronous link with clock recovery and bit skew alignment
Patent number
8,000,351
Issue date
Aug 16, 2011
Juniper Networks, Inc.
David Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Systems and methods for reducing reflections and frequency dependen...
Patent number
7,924,862
Issue date
Apr 12, 2011
Juniper Networks, Inc.
David Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Systems and methods for reducing reflections and frequency dependen...
Patent number
7,724,761
Issue date
May 25, 2010
Juniper Networks, Inc.
David Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Source synchronous link with clock recovery and bit skew alignment
Patent number
7,515,614
Issue date
Apr 7, 2009
Juniper Networks, Inc.
David Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Source synchronous link with clock recovery and bit skew alignment
Patent number
7,061,939
Issue date
Jun 13, 2006
Juniper Networs, Inc.
David Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Redundant source synchronous busses
Patent number
6,646,982
Issue date
Nov 11, 2003
Juniper Networks, Inc.
David Paul Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Multi-loop phase lock loop for controlling jitter in a high frequen...
Patent number
6,538,518
Issue date
Mar 25, 2003
Juniper Networks, Inc.
David Chengson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Processor-inclusive memory module
Patent number
5,999,437
Issue date
Dec 7, 1999
Silicon Graphics, Inc.
David P. Chengson
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Processor-inclusive memory module
Patent number
5,867,419
Issue date
Feb 2, 1999
Silicon Graphics, Inc.
David P. Chengson
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Multi-configurable push-pull/open-drain driver circuit
Patent number
5,811,997
Issue date
Sep 22, 1998
Silicon Graphics, Inc.
David P. Chengson
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Apparatus for generating differential noise between power and groun...
Patent number
5,793,259
Issue date
Aug 11, 1998
Silicon Graphics, Inc.
David Chengson
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
System and method to reduce jitter in digital delay-locked loops
Patent number
5,790,612
Issue date
Aug 4, 1998
Silicon Graphics, Inc.
David P. Chengson
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Processor-inclusive memory module
Patent number
5,710,733
Issue date
Jan 20, 1998
Silicon Graphics, Inc.
David P. Chengson
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
MULTI-INTERFACE COMPATIBLE BUS OVER A COMMON PHYSICAL CONNECTION
Publication number
20130215911
Publication date
Aug 22, 2013
Juniper Networks, Inc.
David P. Chengson
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
VALIDATING HIGH SPEED LINK PERFORMANCE MARGIN FOR SWITCH FABRIC WIT...
Publication number
20110267073
Publication date
Nov 3, 2011
Juniper Networks, Inc.
David P. CHENGSON
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
ERROR-FREE STARTUP OF LOW PHASE NOISE OSCILLATORS
Publication number
20110260769
Publication date
Oct 27, 2011
Juniper Networks, Inc.
David P. CHENGSON
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
SYSTEMS AND METHODS FOR REDUCING REFLECTIONS AND FREQUENCY DEPENDEN...
Publication number
20110158087
Publication date
Jun 30, 2011
Juniper Networks, Inc.
David CHENGSON
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
LOW LATENCY SERIAL MEMORY INTERFACE
Publication number
20110161544
Publication date
Jun 30, 2011
Juniper Networks, Inc.
David P. Chengson
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
SYSTEMS AND METHODS FOR REDUCING REFLECTIONS AND FREQUENCY DEPENDEN...
Publication number
20100118726
Publication date
May 13, 2010
Juniper Networks, Inc.
David CHENGSON
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
SOURCE SYNCHRONOUS LINK WITH CLOCK RECOVERY AND BIT SKEW ALIGNMENT
Publication number
20090168810
Publication date
Jul 2, 2009
Juniper Networks, Inc.
David CHENGSON
H04 - ELECTRIC COMMUNICATION TECHNIQUE