David Sonnier

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic load balancing for multi-core computing environments
- Patent number 11,575,607
- Issue date Feb 7, 2023
- Intel Corporation
- Stephen Palermo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-core communication acceleration using hardware queue device
- Patent number 10,929,323
- Issue date Feb 23, 2021
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core communication acceleration using hardware queue device
- Patent number 10,445,271
- Issue date Oct 15, 2019
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for a distributed hardware queue manager
- Patent number 10,216,668
- Issue date Feb 26, 2019
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data caching in a network communications processor architecture
- Patent number 9,218,290
- Issue date Dec 22, 2015
- Intel Corporation
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking written addresses of a shared memory of a multi-core proce...
- Patent number 9,195,464
- Issue date Nov 24, 2015
- Intel Corporation
- David Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data caching in a network communications processor architecture
- Patent number 9,183,145
- Issue date Nov 10, 2015
- Intel Corporation
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic updating of scheduling hierarchy in a traffic manager of a...
- Patent number 9,160,684
- Issue date Oct 13, 2015
- Intel Corporation
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network based data traffic detection and control
- Patent number 9,154,421
- Issue date Oct 6, 2015
- Intel Corporation
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network communications processor architecture
- Patent number 9,081,742
- Issue date Jul 14, 2015
- Intel Corporation
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Sharing of internal pipeline resources of a network processor with...
- Patent number 8,949,578
- Issue date Feb 3, 2015
- LSI Corporation
- Joseph A. Manzella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multicasting traffic manager in a network communications processor...
- Patent number 8,917,738
- Issue date Dec 23, 2014
- LSI Corporation
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Local messaging in a scheduling hierarchy in a traffic manager of a...
- Patent number 8,869,150
- Issue date Oct 21, 2014
- LSI Corporation
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet draining from a scheduling hierarchy in a traffic manager of...
- Patent number 8,869,151
- Issue date Oct 21, 2014
- LSI Corporation
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scheduling hierarchy in a traffic manager of a network processor
- Patent number 8,848,723
- Issue date Sep 30, 2014
- LSI Corporation
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Shared task parameters in a scheduler of a network processor
- Patent number 8,837,501
- Issue date Sep 16, 2014
- LSI Corporation
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Yield-enhancing device failure analysis
- Patent number 8,738,977
- Issue date May 27, 2014
- Agere Systems LLC
- David A. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for adaptive bandwidth utilization in a digita...
- Patent number 8,718,040
- Issue date May 6, 2014
- Agere Systems LLC
- Deepak Kataria
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for maintaining multicast lists in a data network
- Patent number 8,688,853
- Issue date Apr 1, 2014
- Agere Systems LLC
- David E. Clune
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory manager for a network communications processor architecture
- Patent number 8,677,075
- Issue date Mar 18, 2014
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet draining from a scheduling hierarchy in a traffic manager of...
- Patent number 8,638,805
- Issue date Jan 28, 2014
- LSI Corporation
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Byte-accurate scheduling in a network processor
- Patent number 8,619,787
- Issue date Dec 31, 2013
- LSI Corporation
- David Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet scheduling with guaranteed minimum rate in a traffic manager...
- Patent number 8,615,013
- Issue date Dec 24, 2013
- Agere Systems LLC
- David Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Root scheduling algorithm in a network processor
- Patent number 8,576,862
- Issue date Nov 5, 2013
- LSI Corporation
- David Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multithreaded, superscalar scheduling in a traffic manager of a net...
- Patent number 8,565,250
- Issue date Oct 22, 2013
- LSI Corporation
- Shashank Nemawarkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Task queuing in a network communications processor architecture
- Patent number 8,407,707
- Issue date Mar 26, 2013
- LSI Corporation
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network communications processor architecture with memory load bala...
- Patent number 8,255,644
- Issue date Aug 28, 2012
- LSI Corporation
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible traffic management and shaping processing for multimedia d...
- Patent number 8,214,868
- Issue date Jul 3, 2012
- Agere Systems Inc.
- Christopher W. Hamilton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for updating data structures during in-servic...
- Patent number 7,930,691
- Issue date Apr 19, 2011
- Agere Systems Inc.
- Rajarshi Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual segmentation system and method of operation thereof
- Patent number 7,912,069
- Issue date Mar 22, 2011
- Agere Systems Inc.
- David B. Kramer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS
- Publication number 20240267334
- Publication date Aug 8, 2024
- Intel Corporation
- Stephen Palermo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS
- Publication number 20230231809
- Publication date Jul 20, 2023
- Intel Corporation
- Stephen Palermo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS
- Publication number 20210075730
- Publication date Mar 11, 2021
- Intel Corporation
- Stephen Palermo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE
- Publication number 20200042479
- Publication date Feb 6, 2020
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD BALANCING BASED ON PACKET PROCESSING LOADS
- Publication number 20190253357
- Publication date Aug 15, 2019
- Intel Corporation
- Pravin PATHAK
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR INFLIGHT PACKET COUNT LIMITING IN A QUEUE MANAGER...
- Publication number 20190007318
- Publication date Jan 3, 2019
- Intel Corporation
- Niall D. McDonnell
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR A DISTRIBUTED HARDWARE QUEUE MANAGER
- Publication number 20170286337
- Publication date Oct 5, 2017
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE
- Publication number 20170192921
- Publication date Jul 6, 2017
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING OF INTERNAL PIPELINE RESOURCES OF A NETWORK PROCESSOR WITH...
- Publication number 20120300772
- Publication date Nov 29, 2012
- LSI CORPORATION
- Joseph A. Manzella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20120131283
- Publication date May 24, 2012
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING WRITTEN ADDRESSES OF A SHARED MEMORY OF A MULTI-CORE PROCE...
- Publication number 20120084498
- Publication date Apr 5, 2012
- LSI CORPORATION
- David Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BYTE-ACCURATE SCHEDULING IN A NETWORK PROCESSOR
- Publication number 20120020210
- Publication date Jan 26, 2012
- LSI CORPORATION
- David Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET SCHEDULING WITH GUARANTEED MINIMUM RATE IN A TRAFFIC MANAGER...
- Publication number 20120020223
- Publication date Jan 26, 2012
- LSI CORPORATION
- David Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED TASK PARAMETERS IN A SCHEDULER OF A NETWORK PROCESSOR
- Publication number 20120020250
- Publication date Jan 26, 2012
- LSI CORPORATION
- Balakrishnan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTITHREADED, SUPERSCALAR SCHEDULING IN A TRAFFIC MANAGER OF A NET...
- Publication number 20120020371
- Publication date Jan 26, 2012
- LSI CORPORATION
- Shashank Nemawarkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET DRAINING FROM A SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF...
- Publication number 20120020366
- Publication date Jan 26, 2012
- LSI CORPORATION
- Balakrishnan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC UPDATING OF SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF A...
- Publication number 20120020368
- Publication date Jan 26, 2012
- LSI CORPORATION
- Balakrishnan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROOT SCHEDULING ALGORITHM IN A NETWORK PROCESSOR
- Publication number 20120020370
- Publication date Jan 26, 2012
- LSI CORPORATION
- David Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET DRAINING FROM A SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF...
- Publication number 20120020249
- Publication date Jan 26, 2012
- LSI CORPORATION
- Balakrishnan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF A NETWORK PROCESSOR
- Publication number 20120020369
- Publication date Jan 26, 2012
- LSI CORPORATION
- Balakrishnan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL MESSAGING IN A SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF A...
- Publication number 20120023498
- Publication date Jan 26, 2012
- LSI CORPORATION
- Balakrishnan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICASTING TRAFFIC MANAGER IN A NETWORK COMMUNICATIONS PROCESSOR...
- Publication number 20120002546
- Publication date Jan 5, 2012
- Balakrishnan Sundararaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20110289180
- Publication date Nov 24, 2011
- LSI CORPORATION
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20110289279
- Publication date Nov 24, 2011
- LSI CORPORATION
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TASK QUEUING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20100293353
- Publication date Nov 18, 2010
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network Communications Processor Architecture
- Publication number 20100293312
- Publication date Nov 18, 2010
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE WITH MEMORY LOAD BALA...
- Publication number 20100293345
- Publication date Nov 18, 2010
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Controlling Latency Variation in a Packet...
- Publication number 20080181112
- Publication date Jul 31, 2008
- Juergen Beck
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Yield-Enhancing Device Failure Analysis
- Publication number 20080072118
- Publication date Mar 20, 2008
- David A. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
Network-based data traffic detection and control
- Publication number 20070280125
- Publication date Dec 6, 2007
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

David Sonnier

Person

Patents Grantslast 30 patents

Dynamic load balancing for multi-core computing environments

Multi-core communication acceleration using hardware queue device

Multi-core communication acceleration using hardware queue device

Technologies for a distributed hardware queue manager

Data caching in a network communications processor architecture

Tracking written addresses of a shared memory of a multi-core proce...

Data caching in a network communications processor architecture

Dynamic updating of scheduling hierarchy in a traffic manager of a...

Network based data traffic detection and control

Network communications processor architecture

Sharing of internal pipeline resources of a network processor with...

Multicasting traffic manager in a network communications processor...

Local messaging in a scheduling hierarchy in a traffic manager of a...

Packet draining from a scheduling hierarchy in a traffic manager of...

Scheduling hierarchy in a traffic manager of a network processor

Shared task parameters in a scheduler of a network processor

Yield-enhancing device failure analysis

Method and apparatus for adaptive bandwidth utilization in a digita...

Method and apparatus for maintaining multicast lists in a data network

Memory manager for a network communications processor architecture

Packet draining from a scheduling hierarchy in a traffic manager of...

Byte-accurate scheduling in a network processor

Packet scheduling with guaranteed minimum rate in a traffic manager...

Root scheduling algorithm in a network processor

Multithreaded, superscalar scheduling in a traffic manager of a net...

Task queuing in a network communications processor architecture

Network communications processor architecture with memory load bala...

Flexible traffic management and shaping processing for multimedia d...

Methods and apparatus for updating data structures during in-servic...

Virtual segmentation system and method of operation thereof

Patents Applicationslast 30 patents

DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS

DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS

DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS

MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE

LOAD BALANCING BASED ON PACKET PROCESSING LOADS

TECHNOLOGIES FOR INFLIGHT PACKET COUNT LIMITING IN A QUEUE MANAGER...

TECHNOLOGIES FOR A DISTRIBUTED HARDWARE QUEUE MANAGER

MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE

SHARING OF INTERNAL PIPELINE RESOURCES OF A NETWORK PROCESSOR WITH...

MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

TRACKING WRITTEN ADDRESSES OF A SHARED MEMORY OF A MULTI-CORE PROCE...

BYTE-ACCURATE SCHEDULING IN A NETWORK PROCESSOR

PACKET SCHEDULING WITH GUARANTEED MINIMUM RATE IN A TRAFFIC MANAGER...

SHARED TASK PARAMETERS IN A SCHEDULER OF A NETWORK PROCESSOR

MULTITHREADED, SUPERSCALAR SCHEDULING IN A TRAFFIC MANAGER OF A NET...

PACKET DRAINING FROM A SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF...

DYNAMIC UPDATING OF SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF A...

ROOT SCHEDULING ALGORITHM IN A NETWORK PROCESSOR

PACKET DRAINING FROM A SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF...

SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF A NETWORK PROCESSOR

LOCAL MESSAGING IN A SCHEDULING HIERARCHY IN A TRAFFIC MANAGER OF A...

MULTICASTING TRAFFIC MANAGER IN A NETWORK COMMUNICATIONS PROCESSOR...

DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

TASK QUEUING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

Network Communications Processor Architecture

NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE WITH MEMORY LOAD BALA...

Methods and Apparatus for Controlling Latency Variation in a Packet...

Yield-Enhancing Device Failure Analysis

Network-based data traffic detection and control