David SuitWai Ma

Person

Cary, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Continuous self-calibration of internal analog signals
- Patent number 7,643,956
- Issue date Jan 5, 2010
- Infineon Technologies AG
- David Suitwai Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementation of a fusing scheme to allow internal voltage trimming
- Patent number 7,539,075
- Issue date May 26, 2009
- Infineon Technologies AG
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing one or more dies on a semiconductor w...
- Patent number 7,449,909
- Issue date Nov 11, 2008
- Infineon Technologies AG
- David SuitWai Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuitry wafer
- Patent number 7,330,040
- Issue date Feb 12, 2008
- Infineon Technologies AG
- David Suitwai Ma
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit in a maximum input/output configuration
- Patent number 7,305,594
- Issue date Dec 4, 2007
- Infineon Technologies AG
- James J. Dietz
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementation of a fusing scheme to allow internal voltage trimming
- Patent number 7,277,350
- Issue date Oct 2, 2007
- Infineon Technologies AG
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing one or more dies on a semiconductor w...
- Patent number 7,242,208
- Issue date Jul 10, 2007
- Infineon Technologies AG
- David SuitWai Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Continuous self-calibration of internal analog signals
- Patent number 7,177,373
- Issue date Feb 13, 2007
- Infineon Technologies AG
- David Suitwai Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing one or more dies on a semiconductor w...
- Patent number 7,119,567
- Issue date Oct 10, 2006
- Infineon Technologies North America Corp.
- David SuitWai Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for implementing a power down in a memory device
- Patent number 7,079,441
- Issue date Jul 18, 2006
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Wafer probecard interface
- Patent number 7,071,724
- Issue date Jul 4, 2006
- Infineon Technologies AG
- David Suitwai Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line segmenting in random access memories
- Patent number 6,903,982
- Issue date Jun 7, 2005
- Infineon Technologies AG
- David SuitWai Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for monitoring internal voltages on an integrated...
- Patent number 6,845,048
- Issue date Jan 18, 2005
- Infineon Technologies AG
- George W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Topography correction for testing of redundant array elements
- Patent number 6,754,113
- Issue date Jun 22, 2004
- Infineon Technologies AG
- David Suitwai Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Cooling hood for circuit board
- Patent number 6,721,180
- Issue date Apr 13, 2004
- Infineon Technologies AG
- Thoai-Thai Le
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Leadless socket for decapped semiconductor device
- Patent number 6,702,589
- Issue date Mar 9, 2004
- Infineon Technologies AG
- David SuitWai Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and test method thereof using row compr...
- Patent number 6,667,919
- Issue date Dec 23, 2003
- Infineon Technologies, AG
- David Suitwai Ma
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
IMPLEMENTATION OF A FUSING SCHEME TO ALLOW INTERNAL VOLTAGE TRIMMING
- Publication number 20080008012
- Publication date Jan 10, 2008
- Infineon Technologies AG
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for testing one or more dies on a semiconductor w...
- Publication number 20070152700
- Publication date Jul 5, 2007
- David SuitWai Ma
- G01 - MEASURING TESTING
Information Patent Application
Continuous self-calibration of internal analog signals
- Publication number 20070110145
- Publication date May 17, 2007
- Infineon Technologies AG
- David SuitWai Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementation of a fusing scheme to allow internal voltage trimming
- Publication number 20060274594
- Publication date Dec 7, 2006
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR IMPLEMENTING A POWER DOWN IN A MEMORY DEVICE
- Publication number 20060176751
- Publication date Aug 10, 2006
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for testing one or more dies on a semiconductor w...
- Publication number 20060158209
- Publication date Jul 20, 2006
- Infineon Technologies AG
- David SuitWai Ma
- G01 - MEASURING TESTING
Information Patent Application
Test circuitry wafer
- Publication number 20050285610
- Publication date Dec 29, 2005
- David Suitwai Ma
- G01 - MEASURING TESTING
Information Patent Application
Wafer probecard interface
- Publication number 20050285614
- Publication date Dec 29, 2005
- David Suitwai Ma
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit in a maximum input/output configuration
- Publication number 20040103346
- Publication date May 27, 2004
- Infineon Technologies North America Corp.
- James J. Dietz
- G11 - INFORMATION STORAGE
Information Patent Application
Bit line segmenting in random access memories
- Publication number 20040073745
- Publication date Apr 15, 2004
- Infineon Technologies North America Corp.
- David SuitWai Ma
- G11 - INFORMATION STORAGE
Information Patent Application
Topography correction for testing of redundant array elements
- Publication number 20040057296
- Publication date Mar 25, 2004
- Infineon Technologies North America Corp.
- David Suitwai Ma
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for monitoring internal voltages on an integrated...
- Publication number 20040057289
- Publication date Mar 25, 2004
- Infineon Technologies North America Corp.
- George W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor die isolation system
- Publication number 20040051550
- Publication date Mar 18, 2004
- David Suitwai Ma
- G01 - MEASURING TESTING
Information Patent Application
System and method for testing one or more dies on a semiconductor w...
- Publication number 20040054951
- Publication date Mar 18, 2004
- David SuitWai Ma
- G01 - MEASURING TESTING
Information Patent Application
LEADLESS SOCKET FOR DECAPPED SEMICONDUCTOR DEVICE
- Publication number 20040033707
- Publication date Feb 19, 2004
- Infineon Technologies North America Corp.
- David SuitWai Ma
- G01 - MEASURING TESTING
Information Patent Application
Wordline gate contact for an mbit transistor array layout
- Publication number 20040026763
- Publication date Feb 12, 2004
- David SuitWai Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Continuous self-calibration of internal analog signals
- Publication number 20040028152
- Publication date Feb 12, 2004
- Infineon Technologies North America Corp.
- David SuitWai Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COOLING HOOD FOR CIRCUIT BOARD
- Publication number 20040022024
- Publication date Feb 5, 2004
- Infineon Technologies North America Corp.
- Thoai-Thai Le
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

David SuitWai Ma

Person

Patents Grantslast 30 patents

Continuous self-calibration of internal analog signals

Implementation of a fusing scheme to allow internal voltage trimming

System and method for testing one or more dies on a semiconductor w...

Test circuitry wafer

Integrated circuit in a maximum input/output configuration

Implementation of a fusing scheme to allow internal voltage trimming

System and method for testing one or more dies on a semiconductor w...

Continuous self-calibration of internal analog signals

System and method for testing one or more dies on a semiconductor w...

Methods and apparatus for implementing a power down in a memory device

Wafer probecard interface

Bit line segmenting in random access memories

System and method for monitoring internal voltages on an integrated...

Topography correction for testing of redundant array elements

Cooling hood for circuit board

Leadless socket for decapped semiconductor device

Semiconductor memory device and test method thereof using row compr...

Patents Applicationslast 30 patents

IMPLEMENTATION OF A FUSING SCHEME TO ALLOW INTERNAL VOLTAGE TRIMMING

System and method for testing one or more dies on a semiconductor w...

Continuous self-calibration of internal analog signals

Implementation of a fusing scheme to allow internal voltage trimming

METHODS AND APPARATUS FOR IMPLEMENTING A POWER DOWN IN A MEMORY DEVICE

System and method for testing one or more dies on a semiconductor w...

Test circuitry wafer

Wafer probecard interface

Integrated circuit in a maximum input/output configuration

Bit line segmenting in random access memories

Topography correction for testing of redundant array elements

System and method for monitoring internal voltages on an integrated...

Semiconductor die isolation system

System and method for testing one or more dies on a semiconductor w...

LEADLESS SOCKET FOR DECAPPED SEMICONDUCTOR DEVICE

Wordline gate contact for an mbit transistor array layout

Continuous self-calibration of internal analog signals

COOLING HOOD FOR CIRCUIT BOARD