David T. Blaauw

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for analyzing integrated circuits and apparatus therefor
- Patent number 7,149,674
- Issue date Dec 12, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Supamas Sirichotiyakul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling current demand in an integrate...
- Patent number 6,819,538
- Issue date Nov 16, 2004
- FREESCALE SEMICONDUCTOR, INC.
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross coupling delay characterization for integrated circuits
- Patent number 6,799,153
- Issue date Sep 28, 2004
- FREESCALE SEMICONDUCTOR, INC.
- Supamas Sirichotiyakul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Iterative, noise-sensitive method of routing semiconductor nets usi...
- Patent number 6,480,998
- Issue date Nov 12, 2002
- Motorola, Inc.
- Pradipto Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Waveform manipulation in time warp simulation
- Patent number 6,195,628
- Issue date Feb 27, 2001
- International Business Machines Corporation
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing combinational circuit layout through iterative restructu...
- Patent number 6,074,429
- Issue date Jun 13, 2000
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-transit message detection for global virtual time calculation in...
- Patent number 5,956,261
- Issue date Sep 21, 1999
- International Business Machines Corporation
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimizing element sizes in a semiconductor device
- Patent number 5,903,471
- Issue date May 11, 1999
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating hierarchical DAG representations through a bottom up method
- Patent number 5,790,416
- Issue date Aug 4, 1998
- Motorola, Inc.
- Joseph Wayne Norton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Complementary network reduction for load modeling
- Patent number 5,790,415
- Issue date Aug 4, 1998
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation corrected sensitivity
- Patent number 5,787,008
- Issue date Jul 28, 1998
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accurate delay prediction based on multi-model analysis
- Patent number 5,751,593
- Issue date May 12, 1998
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for the automatic determination of a standard...
- Patent number 5,737,236
- Issue date Apr 7, 1998
- Motorola, Inc.
- Robert Maziasz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design and manufacturing method and an apparatus...
- Patent number 5,689,432
- Issue date Nov 18, 1997
- Motorola, Inc.
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing an integrated circuit
- Patent number 5,666,288
- Issue date Sep 9, 1997
- Motorola, Inc.
- Larry G. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic gate size optimization process for an integrated circuit wher...
- Patent number 5,619,418
- Issue date Apr 8, 1997
- Motorola, Inc.
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Message sequence number control in a virtual time system
- Patent number 5,617,561
- Issue date Apr 1, 1997
- International Business Machines Corporation
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Switching vector generation for electrical circuits
- Publication number 20030061016
- Publication date Mar 27, 2003
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling current demand in an integrate...
- Publication number 20020171407
- Publication date Nov 21, 2002
- David T. Blaauw
- G06 - COMPUTING CALCULATING COUNTING

David T. Blaauw

Person

Patents Grantslast 30 patents

Methods for analyzing integrated circuits and apparatus therefor

Method and apparatus for controlling current demand in an integrate...

Cross coupling delay characterization for integrated circuits

Iterative, noise-sensitive method of routing semiconductor nets usi...

Waveform manipulation in time warp simulation

Optimizing combinational circuit layout through iterative restructu...

In-transit message detection for global virtual time calculation in...

Method for optimizing element sizes in a semiconductor device

Updating hierarchical DAG representations through a bottom up method

Complementary network reduction for load modeling

Simulation corrected sensitivity

Accurate delay prediction based on multi-model analysis

Apparatus and method for the automatic determination of a standard...

Integrated circuit design and manufacturing method and an apparatus...

Method and apparatus for designing an integrated circuit

Logic gate size optimization process for an integrated circuit wher...

Message sequence number control in a virtual time system

Patents Applicationslast 30 patents

Switching vector generation for electrical circuits

Method and apparatus for controlling current demand in an integrate...