Dean Liu

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Repeate architecture with single clock multiplier unit
- Patent number 8,638,896
- Issue date Jan 28, 2014
- NetLogic Microsystems, Inc.
- Dean Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for frequency synthesis with feedback interpo...
- Patent number 8,433,018
- Issue date Apr 30, 2013
- Netlogic Microsystems, Inc.
- Stefanos Sidiropoulos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for a mesochronous transmission system
- Patent number 7,978,802
- Issue date Jul 12, 2011
- Xilinx, Inc.
- Prasun K. Raha
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for receive channel data alignment with minimi...
- Patent number 7,913,104
- Issue date Mar 22, 2011
- Xilinx, Inc.
- Warren E. Cory
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for a programmably terminated receiver
- Patent number 7,724,815
- Issue date May 25, 2010
- Xilinx, Inc.
- Prasun K. Raha
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for minimizing jitter in a clock synthesis ci...
- Patent number 7,436,229
- Issue date Oct 14, 2008
- Net Logic Microsystems, Inc.
- Stefanos Sidiropoulos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for frequency synthesis with feedback interpo...
- Patent number 7,432,750
- Issue date Oct 7, 2008
- NetLogic Microsystems, Inc.
- Stefanos Sidiropoulos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for generating multiple clocks using feedback...
- Patent number 7,323,916
- Issue date Jan 29, 2008
- NetLogic Microsystems, Inc.
- Stefanos Sidiropoulos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus to store delay locked loop biasing parameters
- Patent number 7,251,305
- Issue date Jul 31, 2007
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mixed signal delay locked loop characterization engine
- Patent number 7,136,799
- Issue date Nov 14, 2006
- Sun Microsystems, Inc.
- Kian Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustment and calibration system for post-fabrication treatment of...
- Patent number 7,106,113
- Issue date Sep 12, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating high speed parallel I/O interfaces based on counters
- Patent number 7,062,688
- Issue date Jun 13, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Duty cycle corrector
- Patent number 6,882,196
- Issue date Apr 19, 2005
- Sun Microsystems, Inc.
- Gin Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Jitter estimation for a phase locked loop
- Patent number 6,819,192
- Issue date Nov 16, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design-for-test technique for a delay locked loop
- Patent number 6,815,986
- Issue date Nov 9, 2004
- Sun Microsystems, Inc.
- Aninda Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Increasing power supply noise rejection using linear voltage regula...
- Patent number 6,809,557
- Issue date Oct 26, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G05 - CONTROLLING REGULATING
Information Patent Grant
Quantifying a difference between nodal voltages
- Patent number 6,806,698
- Issue date Oct 19, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for calibrating a delay locked loop charge pum...
- Patent number 6,788,045
- Issue date Sep 7, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Post-silicon phase offset control of phase locked loop input receiver
- Patent number 6,784,752
- Issue date Aug 31, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustment and calibration system for post-fabrication treatment of...
- Patent number 6,768,955
- Issue date Jul 27, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
150 degree bump placement layout for an integrated circuit power grid
- Patent number 6,762,505
- Issue date Jul 13, 2004
- Sun Microsystems
- Sudhakar Bobba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for calibration of a post-fabrication bias vol...
- Patent number 6,753,740
- Issue date Jun 22, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for simulating power supply noise in an on-chip temperature...
- Patent number 6,748,339
- Issue date Jun 8, 2004
- Sun Microsystems, Inc.
- Brian Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop design with diode for loop filter capacitance lea...
- Patent number 6,727,737
- Issue date Apr 27, 2004
- Sun Microsystems, Inc.
- Pradeep Trivedi
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for decoupling capacitor optimization for a temperature sens...
- Patent number 6,704,680
- Issue date Mar 9, 2004
- Sun Microsystems, Inc.
- Brian Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for estimating jitter in a delay locked loop
- Patent number 6,691,291
- Issue date Feb 10, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimizing loop bandwidth in delay locked loops
- Patent number 6,687,881
- Issue date Feb 3, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deskewing global clock skew using localized DLLs
- Patent number 6,686,785
- Issue date Feb 3, 2004
- Sun Microsystems, Inc.
- Dean Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of loop bandwidth for a phase locked loop
- Patent number 6,671,863
- Issue date Dec 30, 2003
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for post-silicon control of delay locked loop charge pump c...
- Patent number 6,664,831
- Issue date Dec 16, 2003
- Sun Microsystems, Inc.
- Claude Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Repeater Architecture with Single Clock Multiplier Unit
- Publication number 20110228889
- Publication date Sep 22, 2011
- Dean Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and Apparatus for Frequency Synthesis with Feedback Interpo...
- Publication number 20080260071
- Publication date Oct 23, 2008
- Stefanos Sidiropoulos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and Apparatus for Minimizing Jitter in a Clock Synthesis Ci...
- Publication number 20080048734
- Publication date Feb 28, 2008
- Stefanos Sidiropoulos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Mixed signal delay locked loop characterization engine
- Publication number 20040183578
- Publication date Sep 23, 2004
- Kian Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Miller effect compensation technique for DLL phase interpolator design
- Publication number 20040169539
- Publication date Sep 2, 2004
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Analog delay locked loop characterization technique
- Publication number 20040017873
- Publication date Jan 29, 2004
- Kian Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Duty cycle corrector
- Publication number 20040012428
- Publication date Jan 22, 2004
- Gin Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Design-for-test technique for a delay locked loop
- Publication number 20040012420
- Publication date Jan 22, 2004
- Aninda Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Updating high speed parallel I/O interfaces based on counters
- Publication number 20040015751
- Publication date Jan 22, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEA...
- Publication number 20040012426
- Publication date Jan 22, 2004
- Pradeep Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for calibration of a post-fabrication bias vol...
- Publication number 20030214362
- Publication date Nov 20, 2003
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustment and calibration system for post-fabrication treatment of...
- Publication number 20030214333
- Publication date Nov 20, 2003
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustment and calibration system for post-fabrication treatment of...
- Publication number 20030215042
- Publication date Nov 20, 2003
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for calibrating a delay locked loop charge pum...
- Publication number 20030214280
- Publication date Nov 20, 2003
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus to store delay locked loop biasing parameters
- Publication number 20030215041
- Publication date Nov 20, 2003
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Post-silicon phase offset control of phase locked loop input receiver
- Publication number 20030201841
- Publication date Oct 30, 2003
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-SILICON CONTROL OF PHASE LOCKED LOOP CHARGE PUMP CURRENT
- Publication number 20030201808
- Publication date Oct 30, 2003
- Claude Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUIT FOR POST-SILICON CONTROL OF DELAY LOCKED LOOP CHARGE PUMP C...
- Publication number 20030201809
- Publication date Oct 30, 2003
- Claude Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for simulating power supply noise in an on-chip temperature...
- Publication number 20030163277
- Publication date Aug 28, 2003
- Brian Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Increasing power supply noise rejection using linear voltage regula...
- Publication number 20030155964
- Publication date Aug 21, 2003
- Claude Gauthier
- G05 - CONTROLLING REGULATING
Information Patent Application
Temperature calibration using on-chip electrical fuses
- Publication number 20030158683
- Publication date Aug 21, 2003
- Claude Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Quantifying a difference between nodal voltages
- Publication number 20030155903
- Publication date Aug 21, 2003
- Claude Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for optimizing loop bandwidth in delay locked loops
- Publication number 20030154447
- Publication date Aug 14, 2003
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimization of loop bandwidth for a phase locked loop
- Publication number 20030154453
- Publication date Aug 14, 2003
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Decoupling capacitor method for a phase locked loop
- Publication number 20030154064
- Publication date Aug 14, 2003
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for estimating jitter in a delay locked loop
- Publication number 20030154454
- Publication date Aug 14, 2003
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for optimizing decoupling capacitor design in delay locked l...
- Publication number 20030154065
- Publication date Aug 14, 2003
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Jitter estimation for a phase locked loop
- Publication number 20030151464
- Publication date Aug 14, 2003
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for decoupling capacitor optimization for a temperature sens...
- Publication number 20030154048
- Publication date Aug 14, 2003
- Brian Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using a push/pull buffer to improve delay locked loop performance
- Publication number 20030132790
- Publication date Jul 17, 2003
- Brian Amick
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Repeate architecture with single clock multiplier unit

Methods and apparatus for frequency synthesis with feedback interpo...

Method and apparatus for a mesochronous transmission system

Method and apparatus for receive channel data alignment with minimi...

Method and apparatus for a programmably terminated receiver

Methods and apparatus for minimizing jitter in a clock synthesis ci...

Methods and apparatus for frequency synthesis with feedback interpo...

Methods and apparatus for generating multiple clocks using feedback...

Method and apparatus to store delay locked loop biasing parameters

Mixed signal delay locked loop characterization engine

Adjustment and calibration system for post-fabrication treatment of...

Updating high speed parallel I/O interfaces based on counters

Duty cycle corrector

Jitter estimation for a phase locked loop

Design-for-test technique for a delay locked loop

Increasing power supply noise rejection using linear voltage regula...

Quantifying a difference between nodal voltages

Method and apparatus for calibrating a delay locked loop charge pum...

Post-silicon phase offset control of phase locked loop input receiver

Adjustment and calibration system for post-fabrication treatment of...

150 degree bump placement layout for an integrated circuit power grid

Method and apparatus for calibration of a post-fabrication bias vol...

Method for simulating power supply noise in an on-chip temperature...

Delay locked loop design with diode for loop filter capacitance lea...

Method for decoupling capacitor optimization for a temperature sens...

Method and system for estimating jitter in a delay locked loop

Method for optimizing loop bandwidth in delay locked loops

Deskewing global clock skew using localized DLLs

Optimization of loop bandwidth for a phase locked loop

Circuit for post-silicon control of delay locked loop charge pump c...

Patents Applicationslast 30 patents

Repeater Architecture with Single Clock Multiplier Unit

Methods and Apparatus for Frequency Synthesis with Feedback Interpo...

Methods and Apparatus for Minimizing Jitter in a Clock Synthesis Ci...

Mixed signal delay locked loop characterization engine

Miller effect compensation technique for DLL phase interpolator design

Analog delay locked loop characterization technique

Duty cycle corrector

Design-for-test technique for a delay locked loop

Updating high speed parallel I/O interfaces based on counters

DELAY LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEA...

Method and apparatus for calibration of a post-fabrication bias vol...

Adjustment and calibration system for post-fabrication treatment of...

Adjustment and calibration system for post-fabrication treatment of...

Method and apparatus for calibrating a delay locked loop charge pum...

Method and apparatus to store delay locked loop biasing parameters

Post-silicon phase offset control of phase locked loop input receiver

POST-SILICON CONTROL OF PHASE LOCKED LOOP CHARGE PUMP CURRENT

CIRCUIT FOR POST-SILICON CONTROL OF DELAY LOCKED LOOP CHARGE PUMP C...

Method for simulating power supply noise in an on-chip temperature...

Increasing power supply noise rejection using linear voltage regula...

Temperature calibration using on-chip electrical fuses

Quantifying a difference between nodal voltages

Method for optimizing loop bandwidth in delay locked loops

Optimization of loop bandwidth for a phase locked loop

Decoupling capacitor method for a phase locked loop

Method and system for estimating jitter in a delay locked loop

Method for optimizing decoupling capacitor design in delay locked l...

Jitter estimation for a phase locked loop

Method for decoupling capacitor optimization for a temperature sens...

Using a push/pull buffer to improve delay locked loop performance