Derek T. Bachand

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low overhead hierarchical connectivity of cache coherent agents to...
- Patent number 10,133,670
- Issue date Nov 20, 2018
- Intel Corporation
- Ramadass Nagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating via an in-die interconnect
- Patent number 8,205,111
- Issue date Jun 19, 2012
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction manager and cache for processing agent
- Patent number 8,122,194
- Issue date Feb 21, 2012
- Intel Corporation
- Chinna Prudvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction manager and cache for processing agent
- Patent number 7,555,603
- Issue date Jun 30, 2009
- Intel Corporation
- Chinna Prudvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 7,487,305
- Issue date Feb 3, 2009
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic priority external transaction system
- Patent number 7,143,242
- Issue date Nov 28, 2006
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 7,133,981
- Issue date Nov 7, 2006
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 6,782,457
- Issue date Aug 24, 2004
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,735,675
- Issue date May 11, 2004
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External bus transaction scheduling system
- Patent number 6,732,242
- Issue date May 4, 2004
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,668,309
- Issue date Dec 23, 2003
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic priority external transaction system
- Patent number 6,654,837
- Issue date Nov 25, 2003
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 6,606,692
- Issue date Aug 12, 2003
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,578,116
- Issue date Jun 10, 2003
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,578,114
- Issue date Jun 10, 2003
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized bus request scheduling mechanism for processing devices
- Patent number 6,499,090
- Issue date Dec 24, 2002
- Intel Corporation
- David L Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,460,119
- Issue date Oct 1, 2002
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,434,677
- Issue date Aug 13, 2002
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction system in a processing agent having minimal delay
- Patent number 6,412,091
- Issue date Jun 25, 2002
- Intel Corporation
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Recycle mechanism for a processing agent
- Patent number 6,401,172
- Issue date Jun 4, 2002
- Intel Corp.
- Chinna Prudvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
“SLIME” cache coherency system for agents with mult...
- Patent number 6,378,048
- Issue date Apr 23, 2002
- Intel Corporation
- Chinna Prudvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Avoiding tag compares during writes in multi-level cache hierarchy
- Patent number 6,321,297
- Issue date Nov 20, 2001
- Intel Corporation
- Gururaj Shamanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction system in a processing agent having minimal delay
- Patent number 6,269,465
- Issue date Jul 31, 2001
- Intel Corporation
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Prefetch queue responsive to read request sequences
- Patent number 6,216,208
- Issue date Apr 10, 2001
- Intel Corporation
- Robert Greiner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read line buffer and signaling protocol for processor
- Patent number 6,209,068
- Issue date Mar 27, 2001
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction stall technique to prevent livelock in multiple-process...
- Patent number 6,078,981
- Issue date Jun 20, 2000
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOW OVERHEAD HIERARCHICAL CONNECTIVITY OF CACHE COHERENT AGENTS TO...
- Publication number 20160188469
- Publication date Jun 30, 2016
- Intel Corporation
- Ramadass Nagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communicating Via An In-Die Interconnect
- Publication number 20100174936
- Publication date Jul 8, 2010
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transaction Manager And Cache For Processing Agent
- Publication number 20100037027
- Publication date Feb 11, 2010
- Chinna Prudvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIORITIZED BUS REQUEST SCHEDULING MECHANISM FOR PROCESSING DEVICES
- Publication number 20070094462
- Publication date Apr 26, 2007
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Early global observation point for a uniprocessor system
- Publication number 20070073977
- Publication date Mar 29, 2007
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prioritized bus request scheduling mechanism for processing devices
- Publication number 20050268051
- Publication date Dec 1, 2005
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic priority external transaction system
- Publication number 20040059854
- Publication date Mar 25, 2004
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prioritized bus request scheduling mechanism for processing devices
- Publication number 20030196050
- Publication date Oct 16, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
External bus transaction scheduling system
- Publication number 20030188107
- Publication date Oct 2, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop blocking for cache coherency
- Publication number 20030115424
- Publication date Jun 19, 2003
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for altering data length to zero to maintain c...
- Publication number 20030110359
- Publication date Jun 12, 2003
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prioritized bus request scheduling mechanism for processing devices
- Publication number 20030018863
- Publication date Jan 23, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop blocking for cache coherency
- Publication number 20020199068
- Publication date Dec 26, 2002
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for altering data length to zero to maintain c...
- Publication number 20020156982
- Publication date Oct 24, 2002
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error correction system in a processing agent having minimal delay
- Publication number 20010020286
- Publication date Sep 6, 2001
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY

Derek T. Bachand

Person

Patents Grantslast 30 patents

Low overhead hierarchical connectivity of cache coherent agents to...

Communicating via an in-die interconnect

Transaction manager and cache for processing agent

Transaction manager and cache for processing agent

Prioritized bus request scheduling mechanism for processing devices

Dynamic priority external transaction system

Prioritized bus request scheduling mechanism for processing devices

Prioritized bus request scheduling mechanism for processing devices

Method and apparatus for altering data length to zero to maintain c...

External bus transaction scheduling system

Snoop blocking for cache coherency

Dynamic priority external transaction system

Prioritized bus request scheduling mechanism for processing devices

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Prioritized bus request scheduling mechanism for processing devices

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Error correction system in a processing agent having minimal delay

Recycle mechanism for a processing agent

&#x0201C;SLIME&#x0201D; cache coherency system for agents with mult...

Avoiding tag compares during writes in multi-level cache hierarchy

Error correction system in a processing agent having minimal delay

Prefetch queue responsive to read request sequences

Read line buffer and signaling protocol for processor

Transaction stall technique to prevent livelock in multiple-process...

Patents Applicationslast 30 patents

LOW OVERHEAD HIERARCHICAL CONNECTIVITY OF CACHE COHERENT AGENTS TO...

Communicating Via An In-Die Interconnect

Transaction Manager And Cache For Processing Agent

PRIORITIZED BUS REQUEST SCHEDULING MECHANISM FOR PROCESSING DEVICES

Early global observation point for a uniprocessor system

Prioritized bus request scheduling mechanism for processing devices

Dynamic priority external transaction system

Prioritized bus request scheduling mechanism for processing devices

External bus transaction scheduling system

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Prioritized bus request scheduling mechanism for processing devices

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Error correction system in a processing agent having minimal delay

“SLIME” cache coherency system for agents with mult...