Diana M. Henderson

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cache array with reduced power consumption
- Patent number 9,977,485
- Issue date May 22, 2018
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache array with reduced power consumption
- Patent number 9,971,394
- Issue date May 15, 2018
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High frequency write through memory device
- Patent number 9,355,692
- Issue date May 31, 2016
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Write/read priority blocking scheme using parallel static address d...
- Patent number 9,281,024
- Issue date Mar 8, 2016
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Write/read priority blocking scheme using parallel static address d...
- Patent number 9,281,025
- Issue date Mar 8, 2016
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM supply voltage global bitline precharge pulse
- Patent number 9,070,433
- Issue date Jun 30, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Increasing memory operating frequency
- Patent number 8,861,284
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Port enable signal generation for gating a memory array device output
- Patent number 8,599,642
- Issue date Dec 3, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Jam latch for latching memory array output data
- Patent number 8,351,278
- Issue date Jan 8, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal bypassing of memory array devices
- Patent number 8,345,497
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Split voltage level restore and evaluate clock signals for memory a...
- Patent number 8,345,490
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...
- Publication number 20150302902
- Publication date Oct 22, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...
- Publication number 20150302908
- Publication date Oct 22, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
CACHE ARRAY WITH REDUCED POWER CONSUMPTION
- Publication number 20150019890
- Publication date Jan 15, 2015
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH FREQUENCY MEMORY
- Publication number 20140078835
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
CACHE ARRAY WITH REDUCED POWER CONSUMPTION
- Publication number 20140082390
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING MEMORY OPERATING FREQUENCY
- Publication number 20140078833
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT
- Publication number 20110320851
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA
- Publication number 20110317496
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY A...
- Publication number 20110317499
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
INTERNAL BYPASSING OF MEMORY ARRAY DEVICES
- Publication number 20110317505
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE

Diana M. Henderson

Person

Patents Grantslast 30 patents

Cache array with reduced power consumption

Cache array with reduced power consumption

High frequency write through memory device

Write/read priority blocking scheme using parallel static address d...

Write/read priority blocking scheme using parallel static address d...

SRAM supply voltage global bitline precharge pulse

Increasing memory operating frequency

Port enable signal generation for gating a memory array device output

Jam latch for latching memory array output data

Internal bypassing of memory array devices

Split voltage level restore and evaluate clock signals for memory a...

Patents Applicationslast 30 patents

WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...

WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS D...

CACHE ARRAY WITH REDUCED POWER CONSUMPTION

HIGH FREQUENCY MEMORY

CACHE ARRAY WITH REDUCED POWER CONSUMPTION

INCREASING MEMORY OPERATING FREQUENCY

PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT

JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA

SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY A...

INTERNAL BYPASSING OF MEMORY ARRAY DEVICES