Dilip Vijay

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Alternate pad structures/passivation inegration schemes to reduce o...
- Patent number 8,552,560
- Issue date Oct 8, 2013
- LSI Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Reduction of macro level stresses in copper/low-K wafers
- Patent number 8,076,779
- Issue date Dec 13, 2011
- LSI Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Patent number 7,531,442
- Issue date May 12, 2009
- LSI Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for avoiding dicing chip-outs in integrated ci...
- Patent number 7,354,790
- Issue date Apr 8, 2008
- LSI Logic Corporation
- Parthasarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduce or eliminate IMC cracking in post wire bonded dies by doping...
- Patent number 7,205,673
- Issue date Apr 17, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of preventing resist poisoning in dual damascene structures
- Patent number 6,969,683
- Issue date Nov 29, 2005
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of preventing resist poisoning in dual damascene structures
- Patent number 6,713,386
- Issue date Mar 30, 2004
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memories with dielectric compositions stable...
- Patent number 6,139,780
- Issue date Oct 31, 2000
- Sharp Kabushiki Kaisha
- Seshu B. Desu
- C04 - CEMENTS CONCRETE ARTIFICIAL STONE CERAMICS REFRACTORIES
Information Patent Grant
Simple method of fabricating ferroelectric capacitors
- Patent number 5,807,774
- Issue date Sep 15, 1998
- Sharp Kabushiki Kaisha
- Seshu B. Desu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High temperature electrode-barriers for ferroelectric and other cap...
- Patent number 5,790,366
- Issue date Aug 4, 1998
- Sharp Kabushiki Kaisha
- Seshu B. Desu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reactive ion etching of lead zirconate titanate and ruthenium oxide...
- Patent number 5,496,437
- Issue date Mar 5, 1996
- CERAM Incorporated
- Seshu B. Desu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming multilayered electrodes for ferroelectric devices...
- Patent number 5,491,102
- Issue date Feb 13, 1996
- CERAM Incorporated
- Seshu B. Desu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE...
- Publication number 20140030541
- Publication date Jan 30, 2014
- LSI Corporation
- Hemanshu Bhatt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Publication number 20070123024
- Publication date May 31, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Alternate pad structures/passivation inegration schemes to reduce o...
- Publication number 20070114667
- Publication date May 24, 2007
- LSI Logic Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Reduction of macro level stresses in copper/Low-K wafers by alterin...
- Publication number 20070102812
- Publication date May 10, 2007
- LSI Logic Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for avoiding dicing chip-outs in integrated ci...
- Publication number 20060160269
- Publication date Jul 20, 2006
- LSI Logic Corporation
- Parthasarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of preventing resist poisoning in dual damascene structures
- Publication number 20040161927
- Publication date Aug 19, 2004
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS

Dilip Vijay

Person

Patents Grantslast 30 patents

Alternate pad structures/passivation inegration schemes to reduce o...

Reduction of macro level stresses in copper/low-K wafers

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Method and apparatus for avoiding dicing chip-outs in integrated ci...

Reduce or eliminate IMC cracking in post wire bonded dies by doping...

Method of preventing resist poisoning in dual damascene structures

Method of preventing resist poisoning in dual damascene structures

Dynamic random access memories with dielectric compositions stable...

Simple method of fabricating ferroelectric capacitors

High temperature electrode-barriers for ferroelectric and other cap...

Reactive ion etching of lead zirconate titanate and ruthenium oxide...

Method of forming multilayered electrodes for ferroelectric devices...

Patents Applicationslast 30 patents

ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE...

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Alternate pad structures/passivation inegration schemes to reduce o...

Reduction of macro level stresses in copper/Low-K wafers by alterin...

Method and apparatus for avoiding dicing chip-outs in integrated ci...

Method of preventing resist poisoning in dual damascene structures