Dmitri Loubychev

Person

Bethlehem, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,617,945
- Issue date Dec 31, 2013
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,143,646
- Issue date Mar 27, 2012
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor buffer architecture for III-V devices on silicon subs...
- Patent number 8,034,675
- Issue date Oct 11, 2011
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor buffer architecture for III-V devices on silicon subs...
- Patent number 7,851,780
- Issue date Dec 14, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,851,781
- Issue date Dec 14, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dopant confinement in the delta doped layer using a dopant segregra...
- Patent number 7,790,536
- Issue date Sep 7, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming buffer layer architecture on silicon and structu...
- Patent number 7,687,799
- Issue date Mar 30, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dopant confinement in the delta doped layer using a dopant segregat...
- Patent number 7,601,980
- Issue date Oct 13, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dislocation-free InSb quantum well structure on Si using novel buff...
- Patent number 7,573,059
- Issue date Aug 11, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer architecture formed on a semiconductor wafer
- Patent number 7,566,898
- Issue date Jul 28, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,494,911
- Issue date Feb 24, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI
- Publication number 20120142166
- Publication date Jun 7, 2012
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBS...
- Publication number 20110045659
- Publication date Feb 24, 2011
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of forming buffer layer architecture on silicon and structu...
- Publication number 20090315018
- Publication date Dec 24, 2009
- Mantu K. Hudait
- B82 - NANO-TECHNOLOGY
Information Patent Application
DOPANT CONFINEMENT IN THE DELTA DOPED LAYER USING A DOPANT SEGREGRA...
- Publication number 20090298266
- Publication date Dec 3, 2009
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20090218596
- Publication date Sep 3, 2009
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer architecture formed on a semiconductor wafer
- Publication number 20080210927
- Publication date Sep 4, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dopant confinement in the delta doped layer using a dopant segregat...
- Publication number 20080157058
- Publication date Jul 3, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dislocation-free InSb quantum well structure on Si using novel buff...
- Publication number 20080073639
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20080076235
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor buffer architecture for III-V devices on silicon subs...
- Publication number 20080029756
- Publication date Feb 7, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacking fault and twin blocking barrier for integrating III-V on Si
- Publication number 20080032478
- Publication date Feb 7, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Depositing polar materials on non-polar semiconductor substrates
- Publication number 20070238281
- Publication date Oct 11, 2007
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS

Dmitri Loubychev

Person

Patents Grantslast 30 patents

Stacking fault and twin blocking barrier for integrating III-V on Si

Stacking fault and twin blocking barrier for integrating III-V on Si

Semiconductor buffer architecture for III-V devices on silicon subs...

Semiconductor buffer architecture for III-V devices on silicon subs...

Buffer layers for device isolation of devices grown on silicon

Dopant confinement in the delta doped layer using a dopant segregra...

Methods of forming buffer layer architecture on silicon and structu...

Dopant confinement in the delta doped layer using a dopant segregat...

Dislocation-free InSb quantum well structure on Si using novel buff...

Buffer architecture formed on a semiconductor wafer

Buffer layers for device isolation of devices grown on silicon

Patents Applicationslast 30 patents

STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI

SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBS...

Methods of forming buffer layer architecture on silicon and structu...

DOPANT CONFINEMENT IN THE DELTA DOPED LAYER USING A DOPANT SEGREGRA...

Buffer layers for device isolation of devices grown on silicon

Buffer architecture formed on a semiconductor wafer

Dopant confinement in the delta doped layer using a dopant segregat...

Dislocation-free InSb quantum well structure on Si using novel buff...

Buffer layers for device isolation of devices grown on silicon

Semiconductor buffer architecture for III-V devices on silicon subs...

Stacking fault and twin blocking barrier for integrating III-V on Si

Depositing polar materials on non-polar semiconductor substrates