Donald A. Evans

Person

Allentown, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual rail single-ended read data paths for static random access mem...
- Patent number 9,177,635
- Issue date Nov 3, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Address decoding circuits for reducing address and memory enable se...
- Patent number 8,923,090
- Issue date Dec 30, 2014
- LSI Corporation
- Donald A. Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting access times to memory cells based on characterized word-...
- Patent number 8,787,099
- Issue date Jul 22, 2014
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting bit-line discharge time in memory arrays based on charact...
- Patent number 8,773,927
- Issue date Jul 8, 2014
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual rail power supply scheme for memories
- Patent number 8,724,421
- Issue date May 13, 2014
- LSI Corporation
- Donald A. Evans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split decode latch with shared feedback
- Patent number 8,610,461
- Issue date Dec 17, 2013
- LSI Corporation
- Richard J. Stephani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory device with area efficient power gating circuitry
- Patent number 8,462,562
- Issue date Jun 11, 2013
- LSI Corporation
- Ankur Goel
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with error correction based on automatic logic inversion
- Patent number 8,365,044
- Issue date Jan 29, 2013
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with phase distribution circuit for controlling relat...
- Patent number 8,284,622
- Issue date Oct 9, 2012
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Generalized BIST for multiport memories
- Patent number 8,201,032
- Issue date Jun 12, 2012
- Agere Systems Inc.
- Donald A. Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Tracking circuit for reducing faults in a memory
- Patent number 8,125,842
- Issue date Feb 28, 2012
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Process and temperature tolerant non-volatile memory
- Patent number 8,059,472
- Issue date Nov 15, 2011
- Agere Systems Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with reduced buffer current during power-down mode
- Patent number 7,933,155
- Issue date Apr 26, 2011
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with redundancy
- Patent number 7,898,887
- Issue date Mar 1, 2011
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit having reduced power consumption
- Patent number 7,848,172
- Issue date Dec 7, 2010
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line driver circuit with reduced leakage
- Patent number 7,826,301
- Issue date Nov 2, 2010
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Process and temperature tolerant non-volatile memory
- Patent number 7,755,948
- Issue date Jul 13, 2010
- Agere Systems Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced leakage driver circuit and memory device employing same
- Patent number 7,633,830
- Issue date Dec 15, 2009
- Agere Systems Inc.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell for content-addressable memory
- Patent number 7,558,095
- Issue date Jul 7, 2009
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port memory
- Patent number 7,551,512
- Issue date Jun 23, 2009
- Agere Systems Inc.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,460,424
- Issue date Dec 2, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Accelerated single-ended sensing for a memory circuit
- Patent number 7,433,254
- Issue date Oct 7, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Accelerated searching for content-addressable memory
- Patent number 7,391,633
- Issue date Jun 24, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memories (CAMs) based on a binary CAM and havin...
- Patent number 7,363,424
- Issue date Apr 22, 2008
- Agere Systems Inc.
- Duane Rodney Aadsen
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout techniques for memory circuitry
- Patent number 7,324,364
- Issue date Jan 29, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding techniques for read-only memory
- Patent number 7,301,828
- Issue date Nov 27, 2007
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memories (CAMs) based on a binary CAM and havin...
- Patent number 7,191,280
- Issue date Mar 13, 2007
- Agere Systems Inc.
- Duane Rodney Aadsen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,177,212
- Issue date Feb 13, 2007
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,085,149
- Issue date Aug 1, 2006
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,042,779
- Issue date May 9, 2006
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES
- Publication number 20150138864
- Publication date May 21, 2015
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES
- Publication number 20150138863
- Publication date May 21, 2015
- LSI Corporation
- Rajiv Kumar Roy
- G11 - INFORMATION STORAGE
Information Patent Application
ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACT...
- Publication number 20140071775
- Publication date Mar 13, 2014
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL RAIL POWER SUPPLY SCHEME FOR MEMORIES
- Publication number 20140025981
- Publication date Jan 23, 2014
- LSI Corporation
- Donald A. Evans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-...
- Publication number 20130343139
- Publication date Dec 26, 2013
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING POWER CONSUMPTION OF MEMORY
- Publication number 20130173944
- Publication date Jul 4, 2013
- LSI CORPORATION
- Ross Kohler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH AREA EFFICIENT POWER GATING CIRCUITRY
- Publication number 20130128676
- Publication date May 23, 2013
- LSI Corporation
- Ankur Goel
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT DECODE LATCH WITH SHARED FEEDBACK
- Publication number 20130076393
- Publication date Mar 28, 2013
- Richard J. Stephani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Device with Phase Distribution Circuit for Controlling Relat...
- Publication number 20120075946
- Publication date Mar 29, 2012
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Process and Temperature Tolerant Non-Volatile Memory
- Publication number 20110222357
- Publication date Sep 15, 2011
- Agerre Systems, Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Tracking Circuit for Reducing Faults in a Memory
- Publication number 20100246293
- Publication date Sep 30, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Reduced Buffer Current During Power-Down Mode
- Publication number 20100220534
- Publication date Sep 2, 2010
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Word Line Driver Circuit with Reduced Leakage
- Publication number 20100165778
- Publication date Jul 1, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Sense Amplifier with Redundancy
- Publication number 20100157707
- Publication date Jun 24, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Circuit Having Reduced Power Consumption
- Publication number 20100128549
- Publication date May 27, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Process and Temperature Tolerant Non-Volatile Memory
- Publication number 20100046291
- Publication date Feb 25, 2010
- Agere Systems, Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Reduced Leakage Driver Circuit and Memory Device Employing Same
- Publication number 20090141580
- Publication date Jun 4, 2009
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Dual-Port Memory
- Publication number 20090034356
- Publication date Feb 5, 2009
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Cell for Content-Addressable Memory
- Publication number 20080273361
- Publication date Nov 6, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Error Correction Based on Automatic Logic Inversion
- Publication number 20080263385
- Publication date Oct 23, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Accelerated Single-Ended Sensing for a Memory Circuit
- Publication number 20080025103
- Publication date Jan 31, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Accelerated Searching for Content-Addressable Memory
- Publication number 20080025119
- Publication date Jan 31, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
GENERALIZED BIST FOR MULTIPORT MEMORIES
- Publication number 20080016418
- Publication date Jan 17, 2008
- Agere Systems Inc.
- Donald A. Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Layout techniques for read-only memory and the like
- Publication number 20070201257
- Publication date Aug 30, 2007
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING TECHNIQUES FOR READ-ONLY MEMORY
- Publication number 20070201281
- Publication date Aug 30, 2007
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Method And Apparatus For Reducing Leakage Current In A Read Only Me...
- Publication number 20070103959
- Publication date May 10, 2007
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORIES (CAMs) BASED ON A BINARY CAM AND HAVIN...
- Publication number 20070103953
- Publication date May 10, 2007
- Agere Systems Inc.
- Duane Rodney Aadsen
- G11 - INFORMATION STORAGE
Information Patent Application
Generalized BIST for multiport memories
- Publication number 20060090106
- Publication date Apr 27, 2006
- Donald A. Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing leakage current in a read only me...
- Publication number 20050162951
- Publication date Jul 28, 2005
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing leakage current in a read only me...
- Publication number 20050162941
- Publication date Jul 28, 2005
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE

Donald A. Evans

Person

Patents Grantslast 30 patents

Dual rail single-ended read data paths for static random access mem...

Address decoding circuits for reducing address and memory enable se...

Adjusting access times to memory cells based on characterized word-...

Adjusting bit-line discharge time in memory arrays based on charact...

Dual rail power supply scheme for memories

Split decode latch with shared feedback

Memory device with area efficient power gating circuitry

Memory device with error correction based on automatic logic inversion

Memory device with phase distribution circuit for controlling relat...

Generalized BIST for multiport memories

Tracking circuit for reducing faults in a memory

Process and temperature tolerant non-volatile memory

Memory device with reduced buffer current during power-down mode

Sense amplifier with redundancy

Memory circuit having reduced power consumption

Word line driver circuit with reduced leakage

Process and temperature tolerant non-volatile memory

Reduced leakage driver circuit and memory device employing same

Memory cell for content-addressable memory

Dual-port memory

Method and apparatus for reducing leakage current in a read only me...

Accelerated single-ended sensing for a memory circuit

Accelerated searching for content-addressable memory

Content addressable memories (CAMs) based on a binary CAM and havin...

Layout techniques for memory circuitry

Decoding techniques for read-only memory

Content addressable memories (CAMs) based on a binary CAM and havin...

Method and apparatus for reducing leakage current in a read only me...

Method and apparatus for reducing leakage current in a read only me...

Method and apparatus for reducing leakage current in a read only me...

Patents Applicationslast 30 patents

MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES

INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES

ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACT...

DUAL RAIL POWER SUPPLY SCHEME FOR MEMORIES

ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-...

REDUCING POWER CONSUMPTION OF MEMORY

MEMORY DEVICE WITH AREA EFFICIENT POWER GATING CIRCUITRY

SPLIT DECODE LATCH WITH SHARED FEEDBACK

Memory Device with Phase Distribution Circuit for Controlling Relat...

Process and Temperature Tolerant Non-Volatile Memory

Tracking Circuit for Reducing Faults in a Memory

Memory Device with Reduced Buffer Current During Power-Down Mode

Word Line Driver Circuit with Reduced Leakage

Sense Amplifier with Redundancy

Memory Circuit Having Reduced Power Consumption

Process and Temperature Tolerant Non-Volatile Memory

Reduced Leakage Driver Circuit and Memory Device Employing Same

Dual-Port Memory

Memory Cell for Content-Addressable Memory

Memory Device with Error Correction Based on Automatic Logic Inversion

Accelerated Single-Ended Sensing for a Memory Circuit

Accelerated Searching for Content-Addressable Memory

GENERALIZED BIST FOR MULTIPORT MEMORIES

Layout techniques for read-only memory and the like

DECODING TECHNIQUES FOR READ-ONLY MEMORY

Method And Apparatus For Reducing Leakage Current In A Read Only Me...

CONTENT ADDRESSABLE MEMORIES (CAMs) BASED ON A BINARY CAM AND HAVIN...

Generalized BIST for multiport memories

Method and apparatus for reducing leakage current in a read only me...

Method and apparatus for reducing leakage current in a read only me...