Doron Orenstien

Person

Haifa, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Instructions and logic to perform mask load and store operations as...
- Patent number 10,120,684
- Issue date Nov 6, 2018
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector mask memory access instructions to perform individual and se...
- Patent number 9,529,592
- Issue date Dec 27, 2016
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Permute operations with flexible zero control
- Patent number 8,909,901
- Issue date Dec 9, 2014
- Intel Corporation
- Cristina Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixing instructions with different register sizes
- Patent number 8,694,758
- Issue date Apr 8, 2014
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed instruction format
- Patent number 8,504,802
- Issue date Aug 6, 2013
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for performing range detection
- Patent number 8,386,547
- Issue date Feb 26, 2013
- Intel Corporation
- Asaf Hargil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a double width load using a single width l...
- Patent number 7,882,325
- Issue date Feb 1, 2011
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power reduction for processor front-end by caching decoded instruct...
- Patent number 7,653,786
- Issue date Jan 26, 2010
- Intel Corporation
- Baruch Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective hardware lock disabling
- Patent number 7,613,908
- Issue date Nov 3, 2009
- Intel Corporation
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for address bus power control
- Patent number 7,216,240
- Issue date May 8, 2007
- Intel Corporation
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power processor hint, such as from a pause instruction
- Patent number 7,159,133
- Issue date Jan 2, 2007
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for data bus power control
- Patent number 7,152,167
- Issue date Dec 19, 2006
- Intel Corporation
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power reduction for processor front-end by caching decoded instruct...
- Patent number 7,130,966
- Issue date Oct 31, 2006
- Intel Corporation
- Baruch Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for communicating between integrated circuits...
- Patent number 7,114,038
- Issue date Sep 26, 2006
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deterministic power-estimation for thermal control
- Patent number 7,096,145
- Issue date Aug 22, 2006
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of processing activity in a multiple core microprocessor
- Patent number 7,043,405
- Issue date May 9, 2006
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power reduction for processor front-end by caching decoded instruct...
- Patent number 6,950,903
- Issue date Sep 27, 2005
- Intel Corporation
- Baruch Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of processing activity across processing hardware base...
- Patent number 6,804,632
- Issue date Oct 12, 2004
- Intel Corporation
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INSTRUCTIONS AND LOGIC TO PERFORM MASK LOAD AND STORE OPERATIONS
- Publication number 20130191615
- Publication date Jul 25, 2013
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED INSTRUCTION FORMAT
- Publication number 20120331271
- Publication date Dec 27, 2012
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and logic for performing range detection
- Publication number 20100115014
- Publication date May 6, 2010
- Asaf Hargil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED INSTRUCTION FORMAT
- Publication number 20090172356
- Publication date Jul 2, 2009
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enabling permute operations with flexible zero control
- Publication number 20090172366
- Publication date Jul 2, 2009
- Cristina Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIXING INSTRUCTIONS WITH DIFFERENT REGISTER SIZES
- Publication number 20090172363
- Publication date Jul 2, 2009
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instructions and logic to perform mask load and store operations
- Publication number 20090172365
- Publication date Jul 2, 2009
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selective hardware lock disabling
- Publication number 20080209172
- Publication date Aug 28, 2008
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power reduction for processor front-end by caching decoded instruct...
- Publication number 20070050554
- Publication date Mar 1, 2007
- Baruch Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power reduction for processor front-end by caching decoded instruct...
- Publication number 20060053245
- Publication date Mar 9, 2006
- Baruch Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distribution of processing activity in a multiple core microprocessor
- Publication number 20050050373
- Publication date Mar 3, 2005
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-power processor hint, such as from a pause instruction
- Publication number 20040148534
- Publication date Jul 29, 2004
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for address bus power control
- Publication number 20040128416
- Publication date Jul 1, 2004
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for address bus power control
- Publication number 20040117671
- Publication date Jun 17, 2004
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for data bus power control
- Publication number 20040117670
- Publication date Jun 17, 2004
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deterministic power-estimation for thermal control
- Publication number 20030125900
- Publication date Jul 3, 2003
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for communicating between integrated circuits...
- Publication number 20030126377
- Publication date Jul 3, 2003
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distribution of processing activity across processing hardware base...
- Publication number 20030110012
- Publication date Jun 12, 2003
- Doron Orenstien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power reduction for processor front-end by caching decoded instruct...
- Publication number 20030009620
- Publication date Jan 9, 2003
- Baruch Solomon
- G06 - COMPUTING CALCULATING COUNTING

Doron Orenstien

Person

Patents Grantslast 30 patents

Instructions and logic to perform mask load and store operations as...

Vector mask memory access instructions to perform individual and se...

Permute operations with flexible zero control

Mixing instructions with different register sizes

Compressed instruction format

Instruction and logic for performing range detection

Method and apparatus for a double width load using a single width l...

Power reduction for processor front-end by caching decoded instruct...

Selective hardware lock disabling

Apparatus and method for address bus power control

Low-power processor hint, such as from a pause instruction

Apparatus and method for data bus power control

Power reduction for processor front-end by caching decoded instruct...

Method and apparatus for communicating between integrated circuits...

Deterministic power-estimation for thermal control

Distribution of processing activity in a multiple core microprocessor

Power reduction for processor front-end by caching decoded instruct...

Distribution of processing activity across processing hardware base...

Patents Applicationslast 30 patents

INSTRUCTIONS AND LOGIC TO PERFORM MASK LOAD AND STORE OPERATIONS

COMPRESSED INSTRUCTION FORMAT

Instruction and logic for performing range detection

COMPRESSED INSTRUCTION FORMAT

Enabling permute operations with flexible zero control

MIXING INSTRUCTIONS WITH DIFFERENT REGISTER SIZES

Instructions and logic to perform mask load and store operations

Selective hardware lock disabling

Power reduction for processor front-end by caching decoded instruct...

Power reduction for processor front-end by caching decoded instruct...

Distribution of processing activity in a multiple core microprocessor

Low-power processor hint, such as from a pause instruction

Apparatus and method for address bus power control

Apparatus and method for address bus power control

Apparatus and method for data bus power control

Deterministic power-estimation for thermal control

Method and apparatus for communicating between integrated circuits...

Distribution of processing activity across processing hardware base...

Power reduction for processor front-end by caching decoded instruct...