Doug Feist

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Fort Collins, CO, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods and structure for on-chip clock jitter testing and analysis
- Patent number 8,619,935
- Issue date Dec 31, 2013
- LSI Corporation
- Douglas J. Feist
- G01 - MEASURING TESTING
Information Patent Grant
High-speed TDF testing on low cost testers using on-chip pulse gene...
- Patent number 7,375,570
- Issue date May 20, 2008
- LSI Logic Corporation
- Kevin Gearhardt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test expansion module
- Patent number 7,240,264
- Issue date Jul 3, 2007
- LSI Corporation
- Kevin J. Gearhardt
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and structure for improved high-speed TDF testing using on-...
- Patent number 7,202,656
- Issue date Apr 10, 2007
- LSI Logic Corporation
- Kevin Gearhardt
- G01 - MEASURING TESTING
Information Patent Grant
Technique for measurement of programmable termination resistor netw...
- Patent number 7,106,074
- Issue date Sep 12, 2006
- LSI Logic Corporation
- Kevin Gearhardt
- G01 - MEASURING TESTING
Information Patent Grant
Analog to digital converter built in self test
- Patent number 7,081,841
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Douglas J. Feist
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS
- Publication number 20140070849
- Publication date Mar 13, 2014
- LSI Corporation
- Douglas J. Feist
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS
- Publication number 20120098571
- Publication date Apr 26, 2012
- LSI Corporation
- Douglas J. Feist
- G01 - MEASURING TESTING
Information Patent Application
High-speed TDF testing on low cost testers using on-chip pulse gene...
- Publication number 20060284665
- Publication date Dec 21, 2006
- LSI Logic Corporation
- Kevin Gearhardt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan test expansion module
- Publication number 20060248418
- Publication date Nov 2, 2006
- Kevin J. Gearhardt
- G01 - MEASURING TESTING
Information Patent Application
Technique for measurement of programmable termination resistor netw...
- Publication number 20060066320
- Publication date Mar 30, 2006
- Kevin Gearhardt
- G01 - MEASURING TESTING