Douglas Blaine Butler

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Twin cell architecture for integrated circuit dynamic random access...
- Patent number 7,916,567
- Issue date Mar 29, 2011
- ProMOS Technologies Pte. Ltd.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched capacitor charge sharing technique for integrated circuit...
- Patent number 7,609,570
- Issue date Oct 27, 2009
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed, low-power input buffer for integrated circuit devices
- Patent number 7,583,110
- Issue date Sep 1, 2009
- ProMOS Technologies Pte. Ltd.
- Douglas Blaine Butler
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh period adjustment technique for dynamic random access memor...
- Patent number 7,515,494
- Issue date Apr 7, 2009
- ProMOS Technologies Pte. Ltd.
- Douglas B. Butler
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory (SRAM) compatible, high availability me...
- Patent number 7,506,100
- Issue date Mar 17, 2009
- United Memories, Inc.
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed, low-power input buffer for integrated circuit devices
- Patent number 7,250,795
- Issue date Jul 31, 2007
- ProMOS Technologies Pte. Ltd.
- Douglas Blaine Butler
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual access DRAM
- Patent number 7,110,306
- Issue date Sep 19, 2006
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power sleep mode operation technique for dynamic random access...
- Patent number 7,099,234
- Issue date Aug 29, 2006
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual word line mode for DRAMs
- Patent number 7,002,874
- Issue date Feb 21, 2006
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-contiguous masked refresh for an integrated circuit memory
- Patent number 6,912,168
- Issue date Jun 28, 2005
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Bandgap reference circuit
- Patent number 6,815,941
- Issue date Nov 9, 2004
- United Memories, Inc.
- Douglas Blaine Butler
- G05 - CONTROLLING REGULATING
Information Patent Grant
Driver timing and circuit technique for a low noise charge pump cir...
- Patent number 6,518,829
- Issue date Feb 11, 2003
- United Memories, Inc.
- Douglas Blaine Butler
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Multi-chip memory apparatus and associated method
- Patent number 6,392,304
- Issue date May 21, 2002
- United Memories, Inc.
- Douglas B. Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for forming a borderless overlapping gate and diffusion c...
- Patent number 6,337,278
- Issue date Jan 8, 2002
- Mosel Vitelic, Inc.
- Douglas Blaine Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Delayed start oscillator circuit
- Patent number 6,317,007
- Issue date Nov 13, 2001
- United Memeories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Planarized integrated circuit product and method for making it
- Patent number 5,811,864
- Issue date Sep 22, 1998
- United Memories, Inc.
- Douglas B. Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and method for accessing memory cells of a memory device
- Patent number 5,680,362
- Issue date Oct 21, 1997
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Sealed self aligned contact process
- Patent number 5,385,634
- Issue date Jan 31, 1995
- Ramtron International Corporation
- Douglas Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Temperature compensated voltage reference for low and wide voltage...
- Patent number 5,315,230
- Issue date May 24, 1994
- United Memories, Inc.
- Michael V. Cordoba
- G05 - CONTROLLING REGULATING
Information Patent Grant
Self sealed aligned contact incorporating a dopant source
- Patent number 5,216,281
- Issue date Jun 1, 1993
- Ramtron Corporation
- Douglas Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked capacitor with sidewall insulation
- Patent number 5,162,890
- Issue date Nov 10, 1992
- Ramtron Corporation
- Douglas B. Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating self-aligned, non-patterned contact areas and s...
- Patent number 5,104,822
- Issue date Apr 14, 1992
- Ramtron Corporation
- Douglas B. Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench capacitor for large scale integrated memory
- Patent number 5,075,817
- Issue date Dec 24, 1991
- Ramtron Corporation
- Douglas B. Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealed self aligned contacts using two nitrides process
- Patent number 5,043,790
- Issue date Aug 27, 1991
- Ramtron Corporation
- Douglas Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric retention method
- Patent number 4,893,272
- Issue date Jan 9, 1990
- Ramtron Corporation
- S. Sheffield Eaton
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistor with low thermal activation energy
- Patent number 4,679,170
- Issue date Jul 7, 1987
- INMOS Corporation
- Ronald R. Bourassa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making polysilicon resistors with a low thermal activatio...
- Patent number 4,560,419
- Issue date Dec 24, 1985
- INMOS Corporation
- Ronald R. Bourassa
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TWIN CELL ARCHITECTURE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS...
- Publication number 20090225613
- Publication date Sep 10, 2009
- PROMOS TECHNOLOGIES PTE.LTD.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY ME...
- Publication number 20090106488
- Publication date Apr 23, 2009
- United Memories, Inc.
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED AREA DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL AND METHOD FO...
- Publication number 20080268646
- Publication date Oct 30, 2008
- ProMOS Technologies PET.LTD.
- Douglas Blaine Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SWITCHED CAPACITOR CHARGE SHARING TECHNIQUE FOR INTEGRATED CIRCUIT...
- Publication number 20080175074
- Publication date Jul 24, 2008
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
REFRESH PERIOD ADJUSTMENT TECHNIQUE FOR DYNAMIC RANDOM ACCESS MEMOR...
- Publication number 20080112248
- Publication date May 15, 2008
- PROMOS TECHNOLOGIES PTE.LTD.
- Douglas B. Butler
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED, LOW-POWER INPUT BUFFER FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20070176650
- Publication date Aug 2, 2007
- PROMOS TECHNOLOGIES PTE.LTD.
- Douglas Blaine Butler
- G11 - INFORMATION STORAGE
Information Patent Application
SHIELDED BITLINE ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORY (DRA...
- Publication number 20070121414
- Publication date May 31, 2007
- PROMOS TECHNOLOGIES PTE.LTD.
- Douglas Blaine Butler
- G11 - INFORMATION STORAGE
Information Patent Application
Reduced area dynamic random access memory (DRAM) cell and method fo...
- Publication number 20070085152
- Publication date Apr 19, 2007
- ProMOS Technologies PTE.LTD. Singapore
- Douglas Blaine Butler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shielded bitline architecture for dynamic random access memory (DRA...
- Publication number 20070058468
- Publication date Mar 15, 2007
- ProMOS Technologies PTE.LTD. Singapore
- Douglas Blaine Butler
- G11 - INFORMATION STORAGE
Information Patent Application
Temperature sensing and monitoring technique for integrated circuit...
- Publication number 20060229839
- Publication date Oct 12, 2006
- United Memories, Inc. Colorado Springs
- Douglas B. Butler
- G01 - MEASURING TESTING
Information Patent Application
High-speed, low-power input buffer for integrated circuit devices
- Publication number 20060220704
- Publication date Oct 5, 2006
- ProMOS Technologies PTE.LTD. Singapore
- Douglas Blaine Butler
- G11 - INFORMATION STORAGE
Information Patent Application
Static random access memory (SRAM) compatible, high availability me...
- Publication number 20060190678
- Publication date Aug 24, 2006
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Static random access memory (SRAM) compatible, high availability me...
- Publication number 20060190676
- Publication date Aug 24, 2006
- United Memories, Inc. Colorado Springs
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache and tag power-down function during low-power data retention s...
- Publication number 20060005053
- Publication date Jan 5, 2006
- Oscar Frederick Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual-port DRAM cell with simultaneous access
- Publication number 20050289293
- Publication date Dec 29, 2005
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Low power sleep mode operation technique for dynamic random access...
- Publication number 20050286339
- Publication date Dec 29, 2005
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Dual access DRAM
- Publication number 20050286291
- Publication date Dec 29, 2005
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit transistor body bias regulation circuit and meth...
- Publication number 20050052219
- Publication date Mar 10, 2005
- Douglas Blaine Butler
- G05 - CONTROLLING REGULATING
Information Patent Application
Non-contiguous masked refresh for an integrated circuit memory
- Publication number 20040184334
- Publication date Sep 23, 2004
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
BANDGAP REFERENCE CIRCUIT
- Publication number 20040150381
- Publication date Aug 5, 2004
- Douglas Blaine Butler
- G05 - CONTROLLING REGULATING
Information Patent Application
DRIVER TIMING AND CIRCUIT TECHNIQUE FOR A LOW NOISE CHARGE PUMP CIR...
- Publication number 20020067201
- Publication date Jun 6, 2002
- Douglas Blaine Butler
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Multi-chip memory apparatus and associated method
- Publication number 20010040281
- Publication date Nov 15, 2001
- Douglas B. Butler
- H01 - BASIC ELECTRIC ELEMENTS

Douglas Blaine Butler

Person

Patents Grantslast 30 patents

Twin cell architecture for integrated circuit dynamic random access...

Switched capacitor charge sharing technique for integrated circuit...

High-speed, low-power input buffer for integrated circuit devices

Refresh period adjustment technique for dynamic random access memor...

Static random access memory (SRAM) compatible, high availability me...

High-speed, low-power input buffer for integrated circuit devices

Dual access DRAM

Low power sleep mode operation technique for dynamic random access...

Dual word line mode for DRAMs

Non-contiguous masked refresh for an integrated circuit memory

Bandgap reference circuit

Driver timing and circuit technique for a low noise charge pump cir...

Multi-chip memory apparatus and associated method

Technique for forming a borderless overlapping gate and diffusion c...

Delayed start oscillator circuit

Planarized integrated circuit product and method for making it

Circuit and method for accessing memory cells of a memory device

Sealed self aligned contact process

Temperature compensated voltage reference for low and wide voltage...

Self sealed aligned contact incorporating a dopant source

Stacked capacitor with sidewall insulation

Method for creating self-aligned, non-patterned contact areas and s...

Trench capacitor for large scale integrated memory

Sealed self aligned contacts using two nitrides process

Ferroelectric retention method

Resistor with low thermal activation energy

Method of making polysilicon resistors with a low thermal activatio...

Patents Applicationslast 30 patents

TWIN CELL ARCHITECTURE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS...

STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY ME...

REDUCED AREA DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL AND METHOD FO...

SWITCHED CAPACITOR CHARGE SHARING TECHNIQUE FOR INTEGRATED CIRCUIT...

REFRESH PERIOD ADJUSTMENT TECHNIQUE FOR DYNAMIC RANDOM ACCESS MEMOR...

HIGH-SPEED, LOW-POWER INPUT BUFFER FOR INTEGRATED CIRCUIT DEVICES

SHIELDED BITLINE ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORY (DRA...

Reduced area dynamic random access memory (DRAM) cell and method fo...

Shielded bitline architecture for dynamic random access memory (DRA...

Temperature sensing and monitoring technique for integrated circuit...

High-speed, low-power input buffer for integrated circuit devices

Static random access memory (SRAM) compatible, high availability me...

Static random access memory (SRAM) compatible, high availability me...

Cache and tag power-down function during low-power data retention s...

Dual-port DRAM cell with simultaneous access

Low power sleep mode operation technique for dynamic random access...

Dual access DRAM

Integrated circuit transistor body bias regulation circuit and meth...

Non-contiguous masked refresh for an integrated circuit memory

BANDGAP REFERENCE CIRCUIT

DRIVER TIMING AND CIRCUIT TECHNIQUE FOR A LOW NOISE CHARGE PUMP CIR...

Multi-chip memory apparatus and associated method