Douglas Oliver Powell

Person

Endicott, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reduced-warpage laminate structure
- Patent number 10,685,919
- Issue date Jun 16, 2020
- International Business Machines Corporation
- Mark C. Lamorey
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Copper feature design for warpage control of substrates
- Patent number 9,659,131
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced-warpage laminate structure
- Patent number 9,613,915
- Issue date Apr 4, 2017
- International Business Machines Corporation
- Mark C. Lamorey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced-warpage laminate structure
- Patent number 9,543,255
- Issue date Jan 10, 2017
- International Business Machines Corporation
- Mark C. Lamorey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial carrier dicing of semiconductor wafers
- Patent number 9,484,239
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial carrier dicing of semiconductor wafers
- Patent number 9,478,453
- Issue date Oct 25, 2016
- International Business Machines Corporation
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper feature design for warpage control of substrates
- Patent number 9,105,535
- Issue date Aug 11, 2015
- International Business Machines Corporation
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Construction of reliable stacked via in electronic substrates—verti...
- Patent number 9,099,458
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Construction of reliable stacked via in electronic substrates—verti...
- Patent number 8,866,026
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Reducing impedance discontinuity in packages
- Patent number 8,791,372
- Issue date Jul 29, 2014
- International Business Machines Corporation
- Paul M. Harvey
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Elastic modulus mapping of a chip carrier in a flip chip package
- Patent number 8,756,546
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Erwin B. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clustered stacked vias for reliable electronic substrates
- Patent number 8,522,430
- Issue date Sep 3, 2013
- International Business Macines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus to reduce impedance discontinuity in packages
- Patent number 8,440,917
- Issue date May 14, 2013
- International Business Machines Corporation
- Paul M. Harvey
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Construction of reliable stacked via in electronic substrates—verti...
- Patent number 8,258,410
- Issue date Sep 4, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Clustered stacked vias for reliable electronic substrates
- Patent number 8,242,593
- Issue date Aug 14, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-layered interconnect structure using liquid crystalline polym...
- Patent number 7,981,245
- Issue date Jul 19, 2011
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Apparatus for crack prevention in integrated circuit packages
- Patent number 7,786,579
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-layered interconnect structure using liquid crystalline polym...
- Patent number 7,777,136
- Issue date Aug 17, 2010
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-layered interconnect structure using liquid crystalline polym...
- Patent number 7,301,108
- Issue date Nov 27, 2007
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Organic dielectric electronic interconnect structures and method fo...
- Patent number 7,253,512
- Issue date Aug 7, 2007
- International Business Machines Corporation
- Douglas O. Powell
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Z-interconnections with liquid crystal polymer dielectric films
- Patent number 7,128,256
- Issue date Oct 31, 2006
- International Business Machines Corporation
- Donald S. Farquhar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Joining member for Z-interconnect in electronic devices without con...
- Patent number 7,083,901
- Issue date Aug 1, 2006
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and structure for small pitch z-axis electrical interconnect...
- Patent number 6,955,849
- Issue date Oct 18, 2005
- International Business Machines Corporation
- Brian E. Curcio
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Organic dielectric electronic interconnect structures and method fo...
- Patent number 6,931,723
- Issue date Aug 23, 2005
- International Business Machines Corporation
- Douglas O. Powell
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for forming a substructure of a multilayered laminate
- Patent number 6,832,436
- Issue date Dec 21, 2004
- International Business Machines Corporation
- Donald O. Anstrom
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-layered interconnect structure using liquid crystalline polym...
- Patent number 6,826,830
- Issue date Dec 7, 2004
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and structure for small pitch z-axis electrical interconnect...
- Patent number 6,790,305
- Issue date Sep 14, 2004
- International Business Machines Corporation
- Brian E. Curcio
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Z-interconnections with liquid crystal polymer dielectric films
- Patent number 6,764,748
- Issue date Jul 20, 2004
- International Business Machines Corporation
- Donald S. Farquhar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multilayered laminate
- Patent number 6,518,516
- Issue date Feb 11, 2003
- International Business Machines Corporation
- Kim J. Blackwell
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated semiconductor package
- Patent number 6,492,715
- Issue date Dec 10, 2002
- International Business Machines Corporation
- Voya R. Markovich
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
REDUCED-WARPAGE LAMINATE STRUCTURE
- Publication number 20170148749
- Publication date May 25, 2017
- International Business Machines Corporation
- Mark C. Lamorey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED-WARPAGE LAMINATE STRUCTURE
- Publication number 20160155708
- Publication date Jun 2, 2016
- International Business Machines Corporation
- Mark C. Lamorey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED-WARPAGE LAMINATE STRUCTURE
- Publication number 20160157357
- Publication date Jun 2, 2016
- International Business Machines Corporation
- Mark C. Lamorey
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Sacrificial Carrier Dicing of Semiconductor Wafers
- Publication number 20160079117
- Publication date Mar 17, 2016
- International Business Machines Corporation
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sacrificial Carrier Dicing of Semiconductor Wafers
- Publication number 20160079111
- Publication date Mar 17, 2016
- International Business Machines Corporation
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Copper Feature Design for Warpage Control of Substrates
- Publication number 20150317423
- Publication date Nov 5, 2015
- International Business Machines Corporation
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE
- Publication number 20140033148
- Publication date Jan 30, 2014
- International Business Machines Corporation
- Erwin B. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Copper Feature Design for Warpage Control of Substrates
- Publication number 20130334711
- Publication date Dec 19, 2013
- International Business Machines Corporation
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus to Reduce Impedance Discontinuity in Packages
- Publication number 20130075148
- Publication date Mar 28, 2013
- IBM Corporation
- Paul M. Harvey
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...
- Publication number 20120299195
- Publication date Nov 29, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES
- Publication number 20120279061
- Publication date Nov 8, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...
- Publication number 20120267158
- Publication date Oct 25, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYM...
- Publication number 20100218891
- Publication date Sep 2, 2010
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Organic Substrate with Asymmetric Thickness for Warp Mitigation
- Publication number 20090265028
- Publication date Oct 22, 2009
- International Business Machines Corporation
- Sri M. Sri-Jayantha
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC...
- Publication number 20090189289
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Karan Kacker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Construction of Reliable Stacked Via in Electronic Substrates - Ver...
- Publication number 20090188705
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES
- Publication number 20090189290
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and Apparatus to Reduce Impedance Discontinuity in Packages
- Publication number 20090126983
- Publication date May 21, 2009
- Paul M. Harvey
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
APPARATUS FOR CRACK PREVENTION IN INTEGRATED CIRCUIT PACKAGES
- Publication number 20080290510
- Publication date Nov 27, 2008
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYM...
- Publication number 20080217050
- Publication date Sep 11, 2008
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYM...
- Publication number 20080178999
- Publication date Jul 31, 2008
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Organic dielectric electronic interconnect structures and method fo...
- Publication number 20050150686
- Publication date Jul 14, 2005
- International Business Machines Corporation
- Douglas O. Powell
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-layered interconnect structure using liquid crystalline polym...
- Publication number 20050057908
- Publication date Mar 17, 2005
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and structure for small pitch z-axis electrical interconnect...
- Publication number 20050008833
- Publication date Jan 13, 2005
- International Business Machines Corporation
- Brian E. Curcio
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Z-interconnections with liquid crystal polymer dielectric films
- Publication number 20040182509
- Publication date Sep 23, 2004
- Donald S. Farquhar
- B32 - LAYERED PRODUCTS
Information Patent Application
Method and structure for small pitch z-axis electrical interconnect...
- Publication number 20040067347
- Publication date Apr 8, 2004
- International Business Machines Corporation
- Brian E. Curcio
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Joining member for Z-interconnect in electronic devices without con...
- Publication number 20040063040
- Publication date Apr 1, 2004
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-layered interconnect structure using liquid crystalline polym...
- Publication number 20030147227
- Publication date Aug 7, 2003
- International Business Machines Corporation
- Frank D. Egitto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multilayered laminate
- Publication number 20020108780
- Publication date Aug 15, 2002
- International Business Machines Corporation
- Kim J. Blackwell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive substructures of a multilayered laminate
- Publication number 20020100613
- Publication date Aug 1, 2002
- International Business Machines Corporation
- Donald O. Anstrom
- H01 - BASIC ELECTRIC ELEMENTS

Douglas Oliver Powell

Person

Patents Grantslast 30 patents

Reduced-warpage laminate structure

Copper feature design for warpage control of substrates

Reduced-warpage laminate structure

Reduced-warpage laminate structure

Sacrificial carrier dicing of semiconductor wafers

Sacrificial carrier dicing of semiconductor wafers

Copper feature design for warpage control of substrates

Construction of reliable stacked via in electronic substrates—verti...

Construction of reliable stacked via in electronic substrates—verti...

Reducing impedance discontinuity in packages

Elastic modulus mapping of a chip carrier in a flip chip package

Clustered stacked vias for reliable electronic substrates

Method and apparatus to reduce impedance discontinuity in packages

Construction of reliable stacked via in electronic substrates—verti...

Clustered stacked vias for reliable electronic substrates

Multi-layered interconnect structure using liquid crystalline polym...

Apparatus for crack prevention in integrated circuit packages

Multi-layered interconnect structure using liquid crystalline polym...

Multi-layered interconnect structure using liquid crystalline polym...

Organic dielectric electronic interconnect structures and method fo...

Z-interconnections with liquid crystal polymer dielectric films

Joining member for Z-interconnect in electronic devices without con...

Method and structure for small pitch z-axis electrical interconnect...

Organic dielectric electronic interconnect structures and method fo...

Method for forming a substructure of a multilayered laminate

Multi-layered interconnect structure using liquid crystalline polym...

Method and structure for small pitch z-axis electrical interconnect...

Z-interconnections with liquid crystal polymer dielectric films

Multilayered laminate

Integrated semiconductor package

Patents Applicationslast 30 patents

REDUCED-WARPAGE LAMINATE STRUCTURE

REDUCED-WARPAGE LAMINATE STRUCTURE

REDUCED-WARPAGE LAMINATE STRUCTURE

Sacrificial Carrier Dicing of Semiconductor Wafers

Sacrificial Carrier Dicing of Semiconductor Wafers

Copper Feature Design for Warpage Control of Substrates

ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE

Copper Feature Design for Warpage Control of Substrates

Method and Apparatus to Reduce Impedance Discontinuity in Packages

CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...

CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES

CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...

MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYM...

Organic Substrate with Asymmetric Thickness for Warp Mitigation

EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC...

Construction of Reliable Stacked Via in Electronic Substrates - Ver...

CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES

Method and Apparatus to Reduce Impedance Discontinuity in Packages

APPARATUS FOR CRACK PREVENTION IN INTEGRATED CIRCUIT PACKAGES

MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYM...

MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYM...

Organic dielectric electronic interconnect structures and method fo...

Multi-layered interconnect structure using liquid crystalline polym...

Method and structure for small pitch z-axis electrical interconnect...

Z-interconnections with liquid crystal polymer dielectric films

Method and structure for small pitch z-axis electrical interconnect...

Joining member for Z-interconnect in electronic devices without con...

Multi-layered interconnect structure using liquid crystalline polym...

Multilayered laminate

Conductive substructures of a multilayered laminate