Douglas W. Kemerer

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Identifying parasitic diode(s) in an integrated circuit physical de...
- Patent number 8,756,554
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Douglas W. Kemerer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying parasitic diode(s) in an integrated circuit physical de...
- Patent number 8,191,030
- Issue date May 29, 2012
- International Business Machines Corporation
- Douglas W. Kemerer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intersect area based ground rule for semiconductor design
- Patent number 7,941,780
- Issue date May 10, 2011
- International Business Machines Corporation
- Albrik Avanessian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for detection and compensation of NBTI induced threshold...
- Patent number 7,849,426
- Issue date Dec 7, 2010
- International Business Machines Corporation
- Kenneth J. Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and circuits to reduce threshold voltage tolerance and skew...
- Patent number 7,696,811
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Corey Kenneth Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to reduce threshold voltage tolerance and skew in multi-thr...
- Patent number 7,671,666
- Issue date Mar 2, 2010
- International Business Machines Corporation
- Corey Kenneth Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable on-chip sense line
- Patent number 7,619,398
- Issue date Nov 17, 2009
- International Business Machines Corporation
- Corey K. Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for detection and compensation of NBTI induced threshold...
- Patent number 7,504,847
- Issue date Mar 17, 2009
- International Business Machines Corporation
- Kenneth J. Goodnow
- G01 - MEASURING TESTING
Information Patent Grant
Identifying parasitic diode(s) in an integrated circuit physical de...
- Patent number 7,490,303
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Douglas W. Kemerer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits to reduce threshold voltage tolerance and skew in multi-th...
- Patent number 7,459,958
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Corey Kenneth Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable on-chip sense line
- Patent number 7,397,228
- Issue date Jul 8, 2008
- International Business Machines Corporation
- Corey K. Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip having a ringed wiring layer interposed bet...
- Patent number 7,146,596
- Issue date Dec 5, 2006
- International Business Machines Corporation
- Thomas R. Bednar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for improving integrated circuit manufacturing pr...
- Patent number 7,076,749
- Issue date Jul 11, 2006
- International Business Machines Corporation
- Douglas W. Kemerer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Support structures for wirebond regions of contact pads over low mo...
- Patent number 6,908,841
- Issue date Jun 21, 2005
- Infineon Technologies AG
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for initializing an integrated circuit using c...
- Patent number 6,577,156
- Issue date Jun 10, 2003
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared ground SRAM cell
- Patent number 6,426,890
- Issue date Jul 30, 2002
- International Business Machines Corporation
- Eric Jasinski
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor wiring technique for reducing electromigration
- Patent number 6,308,302
- Issue date Oct 23, 2001
- International Business Machines Corporation
- David James Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wiring design tool improvement for avoiding electromigration by det...
- Patent number 5,737,580
- Issue date Apr 7, 1998
- International Business Machines Corporation
- David James Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of combining gate array and standard cell circuits on a comm...
- Patent number 5,369,595
- Issue date Nov 29, 1994
- International Business Machines Corporation
- Elliot L. Gould
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of combining gate array and standard cell circuits on a comm...
- Patent number 5,051,917
- Issue date Sep 24, 1991
- International Business Machines Corporation
- Elliot L. Gould
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of combining gate array and standard cell circuits on a comm...
- Patent number 4,786,613
- Issue date Nov 22, 1988
- International Business Machines Corporation
- Elliot L. Gould
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DE...
- Publication number 20130067425
- Publication date Mar 14, 2013
- International Business Machines Corporation
- Douglas W. Kemerer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERSECT AREA BASED GROUND RULE FOR SEMICONDUCTOR DESIGN
- Publication number 20090265673
- Publication date Oct 22, 2009
- International Business Machines Corporation
- Albrik Avanessian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DE...
- Publication number 20090150842
- Publication date Jun 11, 2009
- International Business Machines Corporation
- Douglas W. Kemerer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR DETECTION AND COMPENSATION OF NBTI INDUCED THRESHOLD...
- Publication number 20090113358
- Publication date Apr 30, 2009
- Kenneth J. Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THR...
- Publication number 20080265983
- Publication date Oct 30, 2008
- Corey Kenneth Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW...
- Publication number 20080246533
- Publication date Oct 9, 2008
- Corey Kenneth Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE ON-CHIP SENSE LINE
- Publication number 20080211472
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Corey K. Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods And Circuits To Reduce Threshold Voltage Tolerance and Skew...
- Publication number 20080122524
- Publication date May 29, 2008
- Corey Kenneth Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism For Detection And Compensation Of NBTI Induced Threshold...
- Publication number 20080094092
- Publication date Apr 24, 2008
- Kenneth J Goodnow
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW...
- Publication number 20080086706
- Publication date Apr 10, 2008
- Corey Kenneth Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTACT VIA SCHEME WITH STAGGERED VIAS
- Publication number 20070176295
- Publication date Aug 2, 2007
- International Business Machines Corporation
- Anil K. Chinthakindi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE ON-CHIP SENSE LINE
- Publication number 20070162770
- Publication date Jul 12, 2007
- Corey K. Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPROVING INTEGRATED CIRCUIT MANUFACTURING PR...
- Publication number 20050278663
- Publication date Dec 15, 2005
- International Business Machines Corporation
- Douglas W. Kemerer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Chip Having A Ringed Wiring Layer Interposed Bet...
- Publication number 20050050505
- Publication date Mar 3, 2005
- International Business Machines Corporation
- Thomas R. Bednar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Support structures for wirebond regions of contact pads over low mo...
- Publication number 20040058520
- Publication date Mar 25, 2004
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHARED GROUND SRAM CELL
- Publication number 20020101759
- Publication date Aug 1, 2002
- International Business Machines Corporation
- Eric Jasinski
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for initializing an integrated circuit using c...
- Publication number 20020101777
- Publication date Aug 1, 2002
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE

Douglas W. Kemerer

Person

Patents Grantslast 30 patents

Identifying parasitic diode(s) in an integrated circuit physical de...

Identifying parasitic diode(s) in an integrated circuit physical de...

Intersect area based ground rule for semiconductor design

Mechanism for detection and compensation of NBTI induced threshold...

Methods and circuits to reduce threshold voltage tolerance and skew...

Methods to reduce threshold voltage tolerance and skew in multi-thr...

Programmable on-chip sense line

Mechanism for detection and compensation of NBTI induced threshold...

Identifying parasitic diode(s) in an integrated circuit physical de...

Circuits to reduce threshold voltage tolerance and skew in multi-th...

Programmable on-chip sense line

Integrated circuit chip having a ringed wiring layer interposed bet...

Method and system for improving integrated circuit manufacturing pr...

Support structures for wirebond regions of contact pads over low mo...

Method and apparatus for initializing an integrated circuit using c...

Shared ground SRAM cell

Semiconductor wiring technique for reducing electromigration

Wiring design tool improvement for avoiding electromigration by det...

Method of combining gate array and standard cell circuits on a comm...

Method of combining gate array and standard cell circuits on a comm...

Method of combining gate array and standard cell circuits on a comm...

Patents Applicationslast 30 patents

IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DE...

INTERSECT AREA BASED GROUND RULE FOR SEMICONDUCTOR DESIGN

IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DE...

MECHANISM FOR DETECTION AND COMPENSATION OF NBTI INDUCED THRESHOLD...

METHODS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THR...

METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW...

PROGRAMMABLE ON-CHIP SENSE LINE

Methods And Circuits To Reduce Threshold Voltage Tolerance and Skew...

Mechanism For Detection And Compensation Of NBTI Induced Threshold...

METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW...

CONTACT VIA SCHEME WITH STAGGERED VIAS

PROGRAMMABLE ON-CHIP SENSE LINE

METHOD AND SYSTEM FOR IMPROVING INTEGRATED CIRCUIT MANUFACTURING PR...

Integrated Circuit Chip Having A Ringed Wiring Layer Interposed Bet...

Support structures for wirebond regions of contact pads over low mo...

SHARED GROUND SRAM CELL

Method and apparatus for initializing an integrated circuit using c...