Edmund Blackshear

Person

Wappinger Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-layer circuit using metal layers as a moisture diffusion barr...
- Patent number 10,813,215
- Issue date Oct 20, 2020
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer circuit using metal layers as a moisture diffusion barr...
- Patent number 10,806,030
- Issue date Oct 13, 2020
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip module (MCM) with chip-to-chip connection redundancy and...
- Patent number 10,748,852
- Issue date Aug 18, 2020
- Marvell International Ltd.
- Wolfgang Sauter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer circuit using metal layers as a moisture diffusion barr...
- Patent number 10,687,420
- Issue date Jun 16, 2020
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Photonic die fan out package with edge fiber coupling interface and...
- Patent number 10,598,860
- Issue date Mar 24, 2020
- GLOBALFOUNDRIES Inc.
- Koushik Ramachandran
- G02 - OPTICS
Information Patent Grant
Laminate substrates having radial cut metallic planes
- Patent number 9,818,682
- Issue date Nov 14, 2017
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wiring board with stacked embedded capacitors and method of making
- Patent number 9,743,526
- Issue date Aug 22, 2017
- International Business Machines Corporation
- Edmund Blackshear
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Copper feature design for warpage control of substrates
- Patent number 9,659,131
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for shaping a laminate substrate
- Patent number 9,543,253
- Issue date Jan 10, 2017
- GLOBALFOUNDRIES Inc.
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Constrained die adhesion cure process
- Patent number 9,305,894
- Issue date Apr 5, 2016
- GLOBALFOUNDRIES Inc.
- Edmund Blackshear
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Electronic module assembly with patterned adhesive array
- Patent number 9,293,439
- Issue date Mar 22, 2016
- GLOBALFOUNDRIES Inc.
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for shaping a laminate substrate
- Patent number 9,129,942
- Issue date Sep 8, 2015
- International Business Machines Corporation
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper feature design for warpage control of substrates
- Patent number 9,105,535
- Issue date Aug 11, 2015
- International Business Machines Corporation
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic module assembly with patterned adhesive array
- Patent number 9,093,563
- Issue date Jul 28, 2015
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fixture for shaping a laminate substrate
- Patent number 9,059,240
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for shaping a laminate substrate
- Patent number 9,048,245
- Issue date Jun 2, 2015
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip assembly with a coreless substrate employing a patterned adhes...
- Patent number 9,040,388
- Issue date May 26, 2015
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip assembly with a coreless substrate employing a patterned adhes...
- Patent number 8,378,498
- Issue date Feb 19, 2013
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Quality/reliability system and method in multilevel manufacturing e...
- Patent number 7,174,233
- Issue date Feb 6, 2007
- International Business Machines Corporation
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Overlap stacking of center bus bonded memory chips for double densi...
- Patent number 7,095,104
- Issue date Aug 22, 2006
- International Business Machines Corporation
- Edmund D Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress accommodation in electronic device interconnect technology f...
- Patent number 6,919,515
- Issue date Jul 19, 2005
- International Business Machines Corporation
- Edmund David Blackshear
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Vertically stacked memory chips in FBGA packages
- Patent number 6,774,475
- Issue date Aug 10, 2004
- International Business Machines Corporation
- Edmund D. Blackshear
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-bond encapsulation of area array terminated chip and wafer scal...
- Patent number 6,507,122
- Issue date Jan 14, 2003
- International Business Machines Corporation
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High bandwidth 3D memory packaging technique
- Patent number 6,469,375
- Issue date Oct 22, 2002
- William F. Beausoleil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nickel alloy films for reduced intermetallic formation in solder
- Patent number 6,444,562
- Issue date Sep 3, 2002
- International Business Machines Corporation
- Pedro Armengo Chalco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pre-bond encapsulation of area array terminated chip and wafer scal...
- Patent number 6,312,972
- Issue date Nov 6, 2001
- International Business Machines Corporation
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nickel alloy films for reduced intermetallic formation in solder
- Patent number 6,130,479
- Issue date Oct 10, 2000
- International Business Machines Corporation
- Pedro Armengo Chalco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stirling type cylinder force amplifier
- Patent number 5,095,699
- Issue date Mar 17, 1992
- International Business Machines Corporation
- Edmund D. Blackshear
- F02 - COMBUSTION ENGINES HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS

Patents Applicationslast 30 patents

Information Patent Application
FAN-OUT CONNECTIONS OF PROCESSORS ON A PANEL ASSEMBLY
- Publication number 20190363047
- Publication date Nov 28, 2019
- GLOBALFOUNDRIES INC.
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTONIC DIE FAN OUT PACKAGE WITH EDGE FIBER COUPLING INTERFACE AND...
- Publication number 20190285804
- Publication date Sep 19, 2019
- GLOBALFOUNDRIES INC.
- Koushik Ramachandran
- G02 - OPTICS
Information Patent Application
WIRING BOARD WITH STACKED EMBEDDED CAPACITORS AND METHOD OF MAKING
- Publication number 20170231094
- Publication date Aug 10, 2017
- International Business Machines Corporation
- Edmund Blackshear
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...
- Publication number 20160211481
- Publication date Jul 21, 2016
- Kyocera Circuit Solutions Inc.
- Jean AUDET
- G01 - MEASURING TESTING
Information Patent Application
MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...
- Publication number 20160211229
- Publication date Jul 21, 2016
- Kyocera Circuit Solutions Inc.
- Jean AUDET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...
- Publication number 20160210398
- Publication date Jul 21, 2016
- Kyocera Circuit Solutions Inc.
- Jean AUDET
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRAINED DIE ADHESION CURE PROCESS
- Publication number 20160211161
- Publication date Jul 21, 2016
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAMINATE SUBSTRATES HAVING RADIAL CUT METALLIC PLANES
- Publication number 20160163611
- Publication date Jun 9, 2016
- International Business Machines Corporation
- Edmund Blackshear
- B32 - LAYERED PRODUCTS
Information Patent Application
Copper Feature Design for Warpage Control of Substrates
- Publication number 20150317423
- Publication date Nov 5, 2015
- International Business Machines Corporation
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SHAPING A LAMINATE SUBSTRATE
- Publication number 20150136838
- Publication date May 21, 2015
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC MODULE ASSEMBLY WITH PATTERNED ADHESIVE ARRAY
- Publication number 20150093859
- Publication date Apr 2, 2015
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electronic Module Assembly With Patterned Adhesive Array
- Publication number 20150014836
- Publication date Jan 15, 2015
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONSTRAINED DIE ADHESION CURE PROCESS
- Publication number 20140359995
- Publication date Dec 11, 2014
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Copper Feature Design for Warpage Control of Substrates
- Publication number 20130334711
- Publication date Dec 19, 2013
- International Business Machines Corporation
- Edmund Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SHAPING A LAMINATE SUBSTRATE
- Publication number 20130320578
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIXTURE FOR SHAPING A LAMINATE SUBSTRATE
- Publication number 20130323345
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR SHAPING A LAMINATE SUBSTRATE
- Publication number 20130320069
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHES...
- Publication number 20130157439
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHES...
- Publication number 20120061848
- Publication date Mar 15, 2012
- International Business Machines Corporation
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP CARRIER BEARING LARGE SILICON FOR HIGH PERFORMANCE COMPUTING A...
- Publication number 20100164030
- Publication date Jul 1, 2010
- International Business Machines Corporation
- Stefano S. Oggioni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROLESS NICKEL LEVELING OF LGA PAD SITES FOR HIGH PERFORMANCE O...
- Publication number 20090294971
- Publication date Dec 3, 2009
- International Business Machines Corporation
- Edmund D. BLACKSHEAR
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
IC CHIP PACKAGE SUBSTRATE HAVING OUTERMOST GLASS FIBER REINFORCED E...
- Publication number 20090155552
- Publication date Jun 18, 2009
- International Business Machines Corporation
- Edmund Blackshear
- B32 - LAYERED PRODUCTS
Information Patent Application
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MANAGING TECHNOLOG...
- Publication number 20070187474
- Publication date Aug 16, 2007
- International Business Machines Corporation
- Edmund D. Blackshear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Overlap stacking of center bus bonded memory chips for double densi...
- Publication number 20050110125
- Publication date May 26, 2005
- International Business Machines Corporation
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertically stacked memory chips in FBGA packages
- Publication number 20030137041
- Publication date Jul 24, 2003
- International Business Machines Corporation
- Edmund D. Blackshear
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH BANDWIDTH 3D MEMORY PACKAGING TECHNIQUE
- Publication number 20020117741
- Publication date Aug 29, 2002
- William F. Beausoleil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of a solder joint having a transient liquid phase by anne...
- Publication number 20020092895
- Publication date Jul 18, 2002
- Edmund Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pre-bond encapsulation of area array terminated chip and wafer scal...
- Publication number 20020063342
- Publication date May 30, 2002
- Edmund D. Blackshear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stress accommodation in electronic device interconnect technology f...
- Publication number 20010004943
- Publication date Jun 28, 2001
- Edmund David Blackshear
- H01 - BASIC ELECTRIC ELEMENTS

Edmund Blackshear

Person

Patents Grantslast 30 patents

Multi-layer circuit using metal layers as a moisture diffusion barr...

Multi-layer circuit using metal layers as a moisture diffusion barr...

Multi-chip module (MCM) with chip-to-chip connection redundancy and...

Multi-layer circuit using metal layers as a moisture diffusion barr...

Photonic die fan out package with edge fiber coupling interface and...

Laminate substrates having radial cut metallic planes

Wiring board with stacked embedded capacitors and method of making

Copper feature design for warpage control of substrates

Method for shaping a laminate substrate

Constrained die adhesion cure process

Electronic module assembly with patterned adhesive array

Method for shaping a laminate substrate

Copper feature design for warpage control of substrates

Electronic module assembly with patterned adhesive array

Fixture for shaping a laminate substrate

Method for shaping a laminate substrate

Chip assembly with a coreless substrate employing a patterned adhes...

Chip assembly with a coreless substrate employing a patterned adhes...

Quality/reliability system and method in multilevel manufacturing e...

Overlap stacking of center bus bonded memory chips for double densi...

Stress accommodation in electronic device interconnect technology f...

Vertically stacked memory chips in FBGA packages

Pre-bond encapsulation of area array terminated chip and wafer scal...

High bandwidth 3D memory packaging technique

Nickel alloy films for reduced intermetallic formation in solder

Pre-bond encapsulation of area array terminated chip and wafer scal...

Nickel alloy films for reduced intermetallic formation in solder

Stirling type cylinder force amplifier

Patents Applicationslast 30 patents

FAN-OUT CONNECTIONS OF PROCESSORS ON A PANEL ASSEMBLY

PHOTONIC DIE FAN OUT PACKAGE WITH EDGE FIBER COUPLING INTERFACE AND...

WIRING BOARD WITH STACKED EMBEDDED CAPACITORS AND METHOD OF MAKING

MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...

MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...

MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...

CONSTRAINED DIE ADHESION CURE PROCESS

LAMINATE SUBSTRATES HAVING RADIAL CUT METALLIC PLANES

Copper Feature Design for Warpage Control of Substrates

METHOD FOR SHAPING A LAMINATE SUBSTRATE

ELECTRONIC MODULE ASSEMBLY WITH PATTERNED ADHESIVE ARRAY

Electronic Module Assembly With Patterned Adhesive Array

CONSTRAINED DIE ADHESION CURE PROCESS

Copper Feature Design for Warpage Control of Substrates

METHOD FOR SHAPING A LAMINATE SUBSTRATE

FIXTURE FOR SHAPING A LAMINATE SUBSTRATE

METHOD FOR SHAPING A LAMINATE SUBSTRATE

CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHES...

CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHES...

CHIP CARRIER BEARING LARGE SILICON FOR HIGH PERFORMANCE COMPUTING A...

ELECTROLESS NICKEL LEVELING OF LGA PAD SITES FOR HIGH PERFORMANCE O...

IC CHIP PACKAGE SUBSTRATE HAVING OUTERMOST GLASS FIBER REINFORCED E...

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MANAGING TECHNOLOG...

Overlap stacking of center bus bonded memory chips for double densi...

Vertically stacked memory chips in FBGA packages

HIGH BANDWIDTH 3D MEMORY PACKAGING TECHNIQUE

Formation of a solder joint having a transient liquid phase by anne...

Pre-bond encapsulation of area array terminated chip and wafer scal...

Stress accommodation in electronic device interconnect technology f...