The present invention relates generally to a fixture and more particularly to a fixture for shaping a laminate substrate at chip join temperatures.
High production flip chip organic composite laminate substrates are multi layer structures consisting of alternating layers of conductive metallurgy and dielectric. Dielectric layers may be particle filled organic dielectric (build-up layers) or particle and glass fiber filled organic dielectric (core). Laminate substrates may have length and width in the range of 20 mm to 75 mm, while thickness varies in the range of 0.3 mm to 3 mm. Individual build-up layer thicknesses are in the range of 15 um for copper, 33 um for build-up dielectric and 100 um to 1 mm for core. Laminate substrates have typical build-up dielectric coefficient of thermal expansion (CTE) values of 46 ppm/degree C., and core CTE values of 15 ppm/degree C. Next-generation materials have typical build-up dielectric CTE values of 20 ppm/degree C. and core CTE values of 12 ppm/degree C. Copper material used in composite laminate substrate fabrication is considered to have a CTE value of approximately 17 ppm over the temperature range of interest. Composite CTEs of laminate substrates are in the range of 15 ppm to 20 ppm. Room temperature dielectric loss tangent values of next generation laminate substrate materials are approx. 0.007, which are superior to current production laminates, which have loss tangent values of approximately 0.017.
Due to differential expansion and cure shrinkage of various composite laminate substrate materials during fabrication and use, laminate substrates are non-flat at most temperatures, but may approach a coplanar condition at a single temperature. In particular, laminate substrate silicon chip placement sites, due to high functional wiring density in that location, display strong thermal warpage tendencies over temperature. For best chip assembly yields, it is necessary to control the shape of the chip site during the assembly process. As the temperature of the laminate substrate varies widely during flip chip solder reflow assembly, the shape of the chip site also changes widely. It is necessary to control the shape of the chip site in a non-flat condition to produce a desired range of shapes at solder reflow chip join temperatures for best assembly yields.
In a first aspect of the invention, a method includes providing a laminate substrate. The method includes characterizing the laminate substrate for warpage characteristics. The method includes determining if a correction is needed based on the warpage characteristics. The method includes placing the laminate substrate into a fixture with a necessary correction. The method includes fluxing the laminate substrate. The method further includes placing a chip onto the laminate substrate. The method also includes placing the fixture into a reflow furnace to join the chip and the laminate substrate.
In a further aspect of the invention, a method includes providing a fixture comprising a trap ring, a base plate having a recess adapted to receive a laminate substrate, the base plate including an opening and an adjustable height center button disposed in the opening. The method includes characterizing the laminate substrate for warpage characteristics by using one of room temperature techniques and elevated temperature techniques. The method includes determining if a correction is needed based on the warpage characteristics. The method includes placing a laminate substrate into the fixture with a necessary correction. The method includes fluxing the laminate substrate. The method further includes placing a chip onto the laminate substrate. The method also includes placing the fixture into a reflow furnace to join the chip and the laminate substrate.
In a further aspect of the invention, a fixture includes a trap ring. The fixture further includes a base plate having a recess adapted to receive a laminate substrate, the base plate including an opening. The fixture also includes a center button disposed in the opening.
In a further aspect of the invention, a fixture includes a trap ring. The fixture includes a base plate having a recess adapted to receive a laminate substrate, the base plate including an opening. The fixture further includes a plurality of cavities formed in the recess. The fixture also includes an adjustable height center button disposed in the opening.
The present invention is described in the detailed description below, in reference to the accompanying drawings that depict non-limiting examples of exemplary embodiments of the present invention.
This invention provides a fixture and method for shaping a laminate substrate, such as a flip-chip plastic ball grid array (FCPBGA) laminate substrate, at chip join temperatures. It has been determined that at chip join temperatures, current generation high-volume production laminate substrates are slightly convex in shape. Also, it has been determined that next-generation high-performance laminate substrates are slightly concave in shape. Also, it has been determined that at room temperature, current generation laminate substrates revert to a concave shape, while next generation laminate substrates remain so. This invention achieves a preferred chip site warpage shape in order to maximize chip joining performance and minimize yield loss. The shape of the laminate substrate is controlled to produce an optimum shape over the range of chip join temperatures. The invention shapes the laminate substrate in the chip site region, at the chip join temperatures, to obtain good chip joining yields. It has been determined that for best yields, laminate substrates should be slightly convex, such as from 0 um to 10 um over the chip site area, over the range of chip join solder liquidus temperature.
Referring to
Referring to
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Referring to
The trap ring 60 may be aligned with the base plate 40 by locating features 90 such as dowel pins, a base plate recess depth greater than the laminate substrate and trap ring protrusion into that recess or by other positioning features. The trap ring 60 is coplanar and substantially free of distortion over the temperature range of interest. The trap ring 60 and base plate 40 are fabricated such that movement and distortion of the laminate substrate 10 in the height direction in the coplanar band area are entirely constrained over the temperature range of interest. Outside of the coplanar band area the laminate substrate 10 is free to distort in the height dimension away from the base plate 40, while constrained by the base plate against movement downward. The force exerted by the trap ring 60 against the laminate 10 and base plate coplanar band is limited to the range of none to a few kilograms to enable lateral movement of the laminate in the horizontal direction during thermal expansion.
The center button 70 presents a substantially coplanar surface to the bottom of the laminate substrate 10 over a limited area in its center. Referring to
Referring to
Fixture 86 provides constraint to a coplanar shape in one height direction. Fixture 86 provides freedom to move out of plane in a controlled manner in the other height dimension. Fixture 86 provides freedom to expand in the horizontal direction thermally without constraint such that out of plane distortion is not caused by constrained horizontal thermal expansion.
In mass production, a fixture may be used singly as previously described or in an array 94 or panel size format as shown in
The fixture center button may remain adjustable or may be fixed to an appropriate height as previously determined. The trap ring may remain single, or be in an array format of the size of the fixture pocket. A bottom of a base plate may be formed to perform the function of the trap ring such that fixtures are stackable trays 96 as shown in
Optionally, after incoming measurement, the laminate substrates may be pre-baked to drive out moisture prior to use. The pre-bake may be performed at approximately 130 degree C. for approximately 8 hours. The laminate substrates may be vacuum sealed. The laminate substrates may be stored in nitrogen (N2) prior to use.
In step 120, based on the incoming laminate warpage characteristics measurement in step 110, any needed correction is determined, such as the number of shims 97 required in fixture 200 as shown in
If a given laminate substrate is highly concave, a thicker shim would be used in the fixture to make the laminate substrate more convex during chip joining. If another laminate substrate was slightly concave, a thinner shim, or possibly no shim (as shown in
In step 130 the laminate substrate 10 is placed into the fixture 200 with the proper number of shims 97 for the needed correction that was determined in step 110 (see
In step 140 flux 98 is applied to the laminate substrate 10 prior to chip placement (see
In step 150 bumped chip 25 is placed onto the laminate substrate 10 (see
In step 160 the fixture, including the chip and laminate substrate, is placed into a reflow furnace (not shown) to melt the C4 solder, in the presence of flux, thus joining the chip to the laminate substrate. The chip and the laminate substrate may be joined in a N2 furnace atmosphere at a peak temperature of approximately 235 degree C. to 255 degree C. Typical times above 217 degree C. are approximately 30 seconds to 2 minutes, 30 seconds. Typical ramp up rates and cooling rates are 2 degree C./sec, but can vary.
In step 170, after the chip is joined to the laminate substrate, it is removed from the fixture and sent through a flux cleaning tool. Typical fluxes are water soluble. Flux cleaning is typically a water clean using high pressure water spray nozzles plus drying.
In step 180, the joined chip and laminate substrate warpage may be measured by non-contact optical inspection systems, using tools made by KLA/ICOS, Nikon, RVSI or others that measure coplanarity and warpage or by a non-contact white light reflectometry system such as an FRT tool, or similar means. A sample of joined chip and laminate substrates may also be measured using elevated temperature techniques such as shadow moiré and digital image correlation (DIC). Typical full laminate warpages may be approximately 200 um to 300 um post-chip join. Typical chip site warpages may be approximately 50 um to 100 um post-chip join. Also, a non-destructive X-ray inspection may be performed on the joined chip and laminate substrate to determine the amount of shorts or bridges. Shorting may be used as an indicator of the effectiveness of the fixture according to an embodiment of the invention. If the fixture was optimized by using the proper number of shims (or height of the threaded button) based on incoming laminate warpage data as described previously, then no shorts should be observed after chip join in X-ray inspection. If fixture conditions were not optimized, then shorting may be observed. If the shim (or threaded button) height was too low, causing the laminates to remain concave at chip joining, shorting or bridging of C4's at the chip site periphery may be noticed. If the shim (or threaded button) height was too high, causing the laminate to become too convex at chip join temperatures, excessive shorting may be noted on the center of the chip site area. Opens or nonwets may be observed at the chip site periphery.
After chip join yields have been assured and optimized, subsequent conventional bond and assembly process steps may be performed on the joined chip and laminate substrates. Thus, the incoming laminate substrate measurement, chip join, reflow and re-measurement may be used as an iterative process to determine the optimized fixture conditions for a given laminate substrate form factor. Once determined and optimized, those conditions may be used to run laminate substrates of a given form factor with varying incoming warpages, to achieve joined modules with high chip join yields for the next-generation FCPBGA packages.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
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