Edward Flaherty

Person

Rimes Cottage, GB

People

Patents Grantslast 30 patents

Information Patent Grant
I/O circuitry shared between processor and programmable logic porti...
- Patent number 7,446,561
- Issue date Nov 4, 2008
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded processor with watchdog timer for programmable logic
- Patent number 7,350,178
- Issue date Mar 25, 2008
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded processor with watchdog timer for programmable logic
- Patent number 7,340,596
- Issue date Mar 4, 2008
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration and/or reconfiguration of integrated circuit devices...
- Patent number 7,290,236
- Issue date Oct 30, 2007
- Altera Corporation
- Edward Flaherty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface controller using JTAG scan chain
- Patent number 7,078,929
- Issue date Jul 18, 2006
- Altera Corporation
- Andrew Draper
- G01 - MEASURING TESTING
Information Patent Grant
Distributed bus structure
- Patent number 7,064,578
- Issue date Jun 20, 2006
- Altera Corporation
- Andrew Crosland
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device
- Patent number 7,026,840
- Issue date Apr 11, 2006
- Altera Corporation
- Roger May
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
I/O circuitry shared between processor and programmable logic porti...
- Patent number 6,980,024
- Issue date Dec 27, 2005
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address decoder for programmable logic device
- Patent number 6,937,061
- Issue date Aug 30, 2005
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of hardware and software debuggers
- Patent number 6,826,717
- Issue date Nov 30, 2004
- Altera Corporation
- Andrew Draper
- G01 - MEASURING TESTING
Information Patent Grant
I/O circuitry shared between processor and programmable logic porti...
- Patent number 6,803,785
- Issue date Oct 12, 2004
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus architecture for system on a chip
- Patent number 6,745,369
- Issue date Jun 1, 2004
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration and/or reconfiguration of integrated circuit devices...
- Patent number 6,738,962
- Issue date May 18, 2004
- Altera Corporation
- Edward Flaherty
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
I/O circuitry shared between processor and programmable logic porti...
- Publication number 20060186917
- Publication date Aug 24, 2006
- Altera Corporation, a corporation of Delaware
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bus architecture for system on a chip
- Publication number 20040236893
- Publication date Nov 25, 2004
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING

Edward Flaherty

Person

Patents Grantslast 30 patents

I/O circuitry shared between processor and programmable logic porti...

Embedded processor with watchdog timer for programmable logic

Embedded processor with watchdog timer for programmable logic

Configuration and/or reconfiguration of integrated circuit devices...

Interface controller using JTAG scan chain

Distributed bus structure

Programmable logic device

I/O circuitry shared between processor and programmable logic porti...

Address decoder for programmable logic device

Synchronization of hardware and software debuggers

I/O circuitry shared between processor and programmable logic porti...

Bus architecture for system on a chip

Configuration and/or reconfiguration of integrated circuit devices...

Patents Applicationslast 30 patents

I/O circuitry shared between processor and programmable logic porti...

Bus architecture for system on a chip