Efrain Altamirano Sanchez

Person

Kessel-lo, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Methods of semiconductor device processing
- Patent number 11,527,431
- Issue date Dec 13, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing self-aligned gate and source/drain via connect...
- Patent number 11,430,876
- Issue date Aug 30, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a mask layer
- Patent number 11,430,697
- Issue date Aug 30, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a gate cut structure on an array of semiconduc...
- Patent number 10,978,335
- Issue date Apr 13, 2021
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a pillar structure in a semiconductor layer
- Patent number 10,825,682
- Issue date Nov 3, 2020
- Imec VZW
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Reticles for lithography
- Patent number 10,782,607
- Issue date Sep 22, 2020
- Imec VZW
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Area-selective deposition of a tantalum silicide TaSix mask material
- Patent number 10,784,158
- Issue date Sep 22, 2020
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming micro-pipes on a substrate and a structure formed...
- Patent number 10,493,378
- Issue date Dec 3, 2019
- Imec VZW
- Zheng Tao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Plasma method for reducing post-lithography line width roughness
- Patent number 9,520,298
- Issue date Dec 13, 2016
- Imec VZW
- Peter De Schepper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EUV photoresist encapsulation
- Patent number 8,883,374
- Issue date Nov 11, 2014
- IMEC
- Efrain Altamirano Sanchez
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20240006228
- Publication date Jan 4, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF SEMICONDUCTOR DEVICE PROCESSING
- Publication number 20210193510
- Publication date Jun 24, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING SELF-ALIGNED GATE AND SOURCE/DRAIN VIA CONNECT...
- Publication number 20210126108
- Publication date Apr 29, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20210028059
- Publication date Jan 28, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A MASK LAYER
- Publication number 20200328122
- Publication date Oct 15, 2020
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS OF FORMING A GATE OF A SEMICONDUCTOR DEVICE
- Publication number 20200111892
- Publication date Apr 9, 2020
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Producing a Gate Cut Structure on an Array of Semiconduc...
- Publication number 20200083090
- Publication date Mar 12, 2020
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Area-Selective Deposition of a Mask Material
- Publication number 20190355619
- Publication date Nov 21, 2019
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL CHANNEL DEVICE AND METHOD OF FORMING SAME
- Publication number 20190198643
- Publication date Jun 27, 2019
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reticles for Lithography
- Publication number 20190079384
- Publication date Mar 14, 2019
- IMEC vzw
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method of Forming Micro-pipes on a Substrate and a Structure Formed...
- Publication number 20180043283
- Publication date Feb 15, 2018
- IMEC vzw
- Zheng Tao
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
Information Patent Application
Method for Producing a Pillar Structure in a Semiconductor Layer
- Publication number 20170103889
- Publication date Apr 13, 2017
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Plasma Method for Reducing Post-Lithography Line Width Roughness
- Publication number 20150228497
- Publication date Aug 13, 2015
- Katholieke Universiteit Leuven, K.U.Leuven R&D
- Peter De Schepper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Dopant Implantation of FinFET Structures
- Publication number 20150064889
- Publication date Mar 5, 2015
- IMEC vzw
- Vasile Paraschiv
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EUV Photoresist Encapsulation
- Publication number 20130164657
- Publication date Jun 27, 2013
- IMEC
- Efrain Altamirano Sanchez
- H01 - BASIC ELECTRIC ELEMENTS

Efrain Altamirano Sanchez

Person

Patents Grantslast 30 patents

Methods of semiconductor device processing

Method for producing self-aligned gate and source/drain via connect...

Method of forming a mask layer

Method for producing a gate cut structure on an array of semiconduc...

Method for producing a pillar structure in a semiconductor layer

Reticles for lithography

Area-selective deposition of a tantalum silicide TaSix mask material

Method of forming micro-pipes on a substrate and a structure formed...

Plasma method for reducing post-lithography line width roughness

EUV photoresist encapsulation

Patents Applicationslast 30 patents

Method for Forming a Buried Metal Line in a Semiconductor Substrate

METHODS OF SEMICONDUCTOR DEVICE PROCESSING

METHOD FOR PRODUCING SELF-ALIGNED GATE AND SOURCE/DRAIN VIA CONNECT...

Method for Forming a Buried Metal Line in a Semiconductor Substrate

METHOD OF FORMING A MASK LAYER

PROCESS OF FORMING A GATE OF A SEMICONDUCTOR DEVICE

Method for Producing a Gate Cut Structure on an Array of Semiconduc...

Area-Selective Deposition of a Mask Material

VERTICAL CHANNEL DEVICE AND METHOD OF FORMING SAME

Reticles for Lithography

Method of Forming Micro-pipes on a Substrate and a Structure Formed...

Method for Producing a Pillar Structure in a Semiconductor Layer

Plasma Method for Reducing Post-Lithography Line Width Roughness

Method for Dopant Implantation of FinFET Structures

EUV Photoresist Encapsulation