Eitan Cadouri

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and mechanism for extraction and recognition of polygons in...
- Patent number 8,429,588
- Issue date Apr 23, 2013
- Cadence Design Systems, Inc.
- Anwar Irmatov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for performing partitioning of DRC operations
- Patent number 7,913,206
- Issue date Mar 22, 2011
- Cadence Design Systems, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for extraction and recognition of polygons in...
- Patent number 7,908,579
- Issue date Mar 15, 2011
- Cadence Design Systems, Inc.
- Anwar Irmatov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing parallel processing of electroni...
- Patent number 7,904,852
- Issue date Mar 8, 2011
- Cadence Design Systems, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing parallel processing of electroni...
- Patent number 7,823,095
- Issue date Oct 26, 2010
- Cadence Design Systems, Inc.
- Eitan Cadouri
Information Patent Grant
Method and system for parallel processing of IC design layouts
- Patent number 7,657,856
- Issue date Feb 2, 2010
- Cadence Design Systems, Inc.
- Mathew Koshy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for performing latch-up check on an IC design
- Patent number 7,617,465
- Issue date Nov 10, 2009
- Cadence Design Systems, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for using pattern matching to process an integrat...
- Patent number 7,555,736
- Issue date Jun 30, 2009
- Cadence Design Systems, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjusting die placement on a semiconductor wafer to increase yield
- Patent number 7,508,071
- Issue date Mar 24, 2009
- PDF Solutions, Inc.
- Eitan Cadouri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Mapping yield information of semiconductor dice
- Patent number 7,440,869
- Issue date Oct 21, 2008
- PDF Solutions, Inc.
- Eitan Cadouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and mechanism for performing DRC processing with reduced pas...
- Patent number 7,418,682
- Issue date Aug 26, 2008
- Cadence Design Sysyems, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of die placement on wafers
- Patent number 7,334,205
- Issue date Feb 19, 2008
- PDF Solutions, Inc.
- Eitan Cadouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selecting dice to test using a yield map
- Patent number 7,220,605
- Issue date May 22, 2007
- PDF Solutions, Inc.
- Eitan Cadouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selecting die placement on a semiconductor wafer to reduce test time
- Patent number 7,190,183
- Issue date Mar 13, 2007
- PDF Solutions, Inc.
- Eitan Cadouri
- G01 - MEASURING TESTING
Information Patent Grant
Adjusting die placement on a semiconductor wafer to increase yield
- Patent number 7,169,638
- Issue date Jan 30, 2007
- PDF Solutions, Inc.
- Eitan Cadouri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Transforming yield information of a semiconductor fabrication process
- Patent number 7,039,543
- Issue date May 2, 2006
- PDF Solutions, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of die placement on wafers
- Patent number 6,826,738
- Issue date Nov 30, 2004
- PDF Solutions, Inc.
- Eitan Cadouri
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND MECHANISM FOR EXTRACTION AND RECOGNITION OF POLYGONS IN...
- Publication number 20110167400
- Publication date Jul 7, 2011
- Cadence Design Systems, Inc.
- Anwar Irmatov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND MECHANISM FOR EXTRACTION AND RECOGNITION OF POLYGONS IN...
- Publication number 20070288876
- Publication date Dec 13, 2007
- Cadence Design System, Inc.
- Anwar Irmatov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adjusting die placement on a semiconductor wafer to increase yield
- Publication number 20070105273
- Publication date May 10, 2007
- PDF Solutions, Inc.
- Eitan Cadouri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method and system for using pattern matching to process an integrat...
- Publication number 20060281200
- Publication date Dec 14, 2006
- Cadence Design Systems, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor wafer with non-rectangular shaped dice
- Publication number 20060278956
- Publication date Dec 14, 2006
- PDF Solutions, Inc.
- Eitan Cadouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Optimization of die placement on wafers
- Publication number 20030212966
- Publication date Nov 13, 2003
- WaferYield, Inc.
- Eitan Cadouri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Eitan Cadouri

Person

Patents Grantslast 30 patents

Method and mechanism for extraction and recognition of polygons in...

Method and mechanism for performing partitioning of DRC operations

Method and mechanism for extraction and recognition of polygons in...

Method and system for implementing parallel processing of electroni...

Method and system for implementing parallel processing of electroni...

Method and system for parallel processing of IC design layouts

Method and mechanism for performing latch-up check on an IC design

Method and system for using pattern matching to process an integrat...

Adjusting die placement on a semiconductor wafer to increase yield

Mapping yield information of semiconductor dice

Method and mechanism for performing DRC processing with reduced pas...

Optimization of die placement on wafers

Selecting dice to test using a yield map

Selecting die placement on a semiconductor wafer to reduce test time

Adjusting die placement on a semiconductor wafer to increase yield

Transforming yield information of a semiconductor fabrication process

Optimization of die placement on wafers

Patents Applicationslast 30 patents

METHOD AND MECHANISM FOR EXTRACTION AND RECOGNITION OF POLYGONS IN...

METHOD AND MECHANISM FOR EXTRACTION AND RECOGNITION OF POLYGONS IN...

Adjusting die placement on a semiconductor wafer to increase yield

Method and system for using pattern matching to process an integrat...

Semiconductor wafer with non-rectangular shaped dice

Optimization of die placement on wafers