1. Field of the Invention
The present application relates generally to integrated circuit design and fabrication on a semiconductor wafer and, more particularly, to fabricating non-rectangular dice among a plurality of saw streets on a semiconductor wafer.
2. Related Art
In semiconductor wafer processing, integrated circuits (ICs) are formed on a semiconductor wafer. In general, layers of various materials, which are either semiconducting, conducting or insulating, are utilized to form the ICs. These materials are doped, deposited and etched using various well-known processes to form the ICs. Each semiconductor wafer is processed to form a large number of individual regions containing ICs known as dice. Test circuits, test pads and alignment markings may also be formed on the wafer in regions between the dice referred to as saw streets.
Following the integrated circuit formation process and before dice are separated, a full wafer may be tested. While multiple dice are attached together on a single wafer, semiconductor manufactures often perform wafer level testing of the dice. The test circuits and test pads formed in the saw streets between the dice are used to assist in performing the wafer level testing of the dice. Wafer level testing identifies bad dice before further effort is expended in testing and packaging. Therefore, wafer level testing allows a manufacturer to identify and discard unsatisfactory dice.
Following testing, the wafer is diced to separate the individual dice from one another for packaging or for use in an unpackaged form within larger circuits. Two techniques for wafer dicing include scribing and sawing. With scribing, a diamond tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the saw street between the dice. Any test circuits, test pads and alignment marks positioned in a saw street are sacrificed. Thus, these structures can be referred to as sacrificial structures.
As mask layout tolerances decrease and cutting techniques improve, there may also be a corresponding decrease in distance between individual dice on a semiconductor wafer. Therefore, the width of the saw streets between individual dice may also narrow. The resulting saw streets may leave little room for sacrificial structures.
In one exemplary embodiment, a semiconductor wafer has a plurality of dice formed on the wafer. The plurality of dice having non-rectangular shapes with at least one notched corner. A plurality of saw streets are defined between the plurality of dice. At an intersection of two of the plurality of saw streets, a distance is defined between corners of two adjacent dice that is greater than a minimum distance between the two adjacent dice.
The present application can be best understood by reference to the following description taken in conjunction with the accompanying drawing figures, in which like parts may be referred to by like numerals:
The following description sets forth numerous specific configurations, parameters, and the like. It should be recognized, however, that such description is not intended as a limitation on the scope of the present invention, but is instead provided as a description of exemplary embodiments.
Circuit designers provide circuit pattern data, which describes a particular IC design, to a reticle production system, or reticle writer. The circuit pattern data is typically in the form of a representational layout of the physical layers of the fabricated IC device. The representational layout typically includes a representational layer for each physical layer of the IC device (e.g., gate oxide, polysilicon, metallization, etc.). The representational layout may also include one or more representational layers defining structures positioned over sacrificial areas (e.g., over saw streets). These sacrificial structures may include alignment markings, identification markings, measurement markings, test pads, test circuitry, and the like.
The reticle writer uses the circuit pattern data to write (e.g., using an electron beam writer or laser scanner to expose a reticle pattern) a plurality of reticles that will later be used to fabricate the particular IC design and sacrificial structures.
A reticle or photomask is an optical element containing at least transparent and opaque regions, and sometimes semi-transparent and phase shifting regions, as well, which together define the pattern of coplanar features in an electronic device such as an IC and sacrificial structures. Reticles are used during a photolithographic process to define specified regions of a semiconductor wafer for etching, ion implantation, or other fabrication process. For many modern IC designs, an optical reticle's features are between about one and about five times larger than the corresponding features on the wafer. For other exposure systems (e.g., x-ray, e-beam, and extreme ultraviolet) a similar range of reduction ratios also apply.
A single wafer may be divided along boundaries between the individual devices by scoring or cutting along axes referred to as scribe lines in the saw streets. Some or all of the sacrificial structures may be destroyed during dicing. Separation or dicing may be performed by sawing, laser cutting, and the like.
In the present exemplary embodiment, die images 101-109 also have at least one side not parallel to saw street regions 61, 62. Note that because die images 101-109 have non-rectangular shapes, saw street regions 61, 62 are non-rectilinear. In
As depicted in
In the present exemplary embodiment, dice 111-114 also have at least one side not parallel to saw streets 71, 72. Note that because dice 111-114 have non-rectangular shapes, saw streets 71, 72 are non-rectilinear. In
Additionally, sacrificial structures 210 are formed on the wafer from sacrificial structure images 200 (
Although dice 111-114 are depicted as having an octagonal shape, it should be recognized that dice 111-114 can have various non-rectangular shapes, such as hexagonal shapes. For example,
Although exemplary embodiments have been described, various modifications can be made without departing from the spirit and/or scope of the present invention. Therefore, the present invention should not be construed as being limited to the specific forms shown in the drawings and described above.
This application claims the benefit of U.S. Provisional Application No. 60/453,921, titled A PROCESS OF BETTER DESIGNING RETICLE FIELDS, filed Mar. 13, 2003, the entire content of which is incorporated herein by reference.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/US04/07827 | 3/12/2004 | WO | 9/8/2005 |
Number | Date | Country | |
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60453921 | Mar 2003 | US |