Elmoustapha Ould-Ahmed-Vall

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction execution that broadcasts and masks data values at diff...
- Patent number 12,197,617
- Issue date Jan 14, 2025
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for tile load, multiplication and...
- Patent number 12,182,571
- Issue date Dec 31, 2024
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for computing dot products of nibbles in two ti...
- Patent number 12,182,568
- Issue date Dec 31, 2024
- Intel Corporation
- Raanan Sade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,182,035
- Issue date Dec 31, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent multi-datatype execution within a processing resource
- Patent number 12,175,252
- Issue date Dec 24, 2024
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for performing matrix compress and decompress i...
- Patent number 12,175,246
- Issue date Dec 24, 2024
- Intel Corporation
- Dan Baum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for instructions to multiply valu...
- Patent number 12,153,920
- Issue date Nov 26, 2024
- Intel Corporation
- Mohamed Elmalaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for tile matrix multiplication an...
- Patent number 12,147,804
- Issue date Nov 19, 2024
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute optimizations for low precision machine learning operations
- Patent number 12,148,063
- Issue date Nov 19, 2024
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for a processor architecture
- Patent number 12,130,740
- Issue date Oct 29, 2024
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for addition of partial products
- Patent number 12,124,846
- Issue date Oct 22, 2024
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,124,383
- Issue date Oct 22, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for tile transpose
- Patent number 12,124,847
- Issue date Oct 22, 2024
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 12,117,962
- Issue date Oct 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable coarse grained and sparse matrix compute hardware with...
- Patent number 12,112,397
- Issue date Oct 8, 2024
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for matrix operations
- Patent number 12,106,100
- Issue date Oct 1, 2024
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 12,086,594
- Issue date Sep 10, 2024
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional adjustment of render rate
- Patent number 12,061,831
- Issue date Aug 13, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,056,059
- Issue date Aug 6, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression of machine learning models utilizing pseudo-labeled dat...
- Patent number 12,056,906
- Issue date Aug 6, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Specialized fixed function hardware for efficient convolution
- Patent number 12,050,984
- Issue date Jul 30, 2024
- Intel Corporation
- Rajkishore Barik
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD
- Publication number 20250004716
- Publication date Jan 2, 2025
- Intel Corporation
- Robert VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS
- Publication number 20250004763
- Publication date Jan 2, 2025
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240427600
- Publication date Dec 26, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS
- Publication number 20240404487
- Publication date Dec 5, 2024
- Intel Corporation
- Louis Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING ACCELERATOR MECHANISM
- Publication number 20240403620
- Publication date Dec 5, 2024
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS
- Publication number 20240385975
- Publication date Nov 21, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20240354043
- Publication date Oct 24, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS SYSTEM WITH ADDITIONAL CONTEXT
- Publication number 20240355032
- Publication date Oct 24, 2024
- Intel Corporation
- Atsuo Kuwahara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPPARATUS FOR MATRIX MOVE
- Publication number 20240320001
- Publication date Sep 26, 2024
- Intel Corporation
- Robert VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE
- Publication number 20240256276
- Publication date Aug 1, 2024
- Intel Corporation
- Robert VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20240256456
- Publication date Aug 1, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM
- Publication number 20240256825
- Publication date Aug 1, 2024
- Intel Corporation
- Liwei Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS
- Publication number 20240192954
- Publication date Jun 13, 2024
- Intel Corporation
- Robert VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20240184739
- Publication date Jun 6, 2024
- Intel Corporation
- Joydeep RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT
- Publication number 20240161226
- Publication date May 16, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS
- Publication number 20240143325
- Publication date May 2, 2024
- Intel Corporation
- Raanan Sade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS TO STORE A TILE REGISTER PAIR TO MEMORY
- Publication number 20240143328
- Publication date May 2, 2024
- Intel Corporation
- Raanan Sade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MUL...
- Publication number 20240134644
- Publication date Apr 25, 2024
- Intel Corporation
- Robert VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION...
- Publication number 20240126546
- Publication date Apr 18, 2024
- Intel Corporation
- Roman S. Dubtsov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILE...
- Publication number 20240126551
- Publication date Apr 18, 2024
- Intel Corporation
- Bret TOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILE...
- Publication number 20240103867
- Publication date Mar 28, 2024
- Intel Corporation
- Bret TOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...
- Publication number 20240086357
- Publication date Mar 14, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES
- Publication number 20240086356
- Publication date Mar 14, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20240086138
- Publication date Mar 14, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING

Elmoustapha Ould-Ahmed-Vall

Person

Patents Grantslast 30 patents

Systems and methods for improving cache efficiency and utilization

Graphics processor data access and sharing

Instruction execution that broadcasts and masks data values at diff...

Multi-tile memory management

Systems, methods, and apparatuses for tile load, multiplication and...

Systems and methods for computing dot products of nibbles in two ti...

Systems and methods for cache optimization

Concurrent multi-datatype execution within a processing resource

Systems and methods for performing matrix compress and decompress i...

Apparatuses, methods, and systems for instructions to multiply valu...

Cache structure and utilization

Systems, methods, and apparatuses for tile matrix multiplication an...

Compute optimizations for low precision machine learning operations

Systolic disaggregation within a matrix accelerator architecture

Apparatuses and methods for a processor architecture

Systems, apparatuses, and methods for addition of partial products

Systems and methods for cache optimization

Systems, methods, and apparatuses for tile transpose

Scalar core integration

Programmable coarse grained and sparse matrix compute hardware with...

Systems, methods, and apparatuses for matrix operations

Multi-tile memory management

Compression techniques

Vector friendly instruction format and execution thereof

Graphics processor operation scheduling for deterministic latency

Cache structure and utilization

Regional adjustment of render rate

Systems and methods for cache optimization

Compression of machine learning models utilizing pseudo-labeled dat...

Specialized fixed function hardware for efficient convolution

Patents Applicationslast 30 patents

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

CACHE STRUCTURE AND UTILIZATION

COMPRESSION TECHNIQUES

GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS

MACHINE LEARNING ACCELERATOR MECHANISM

EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS

Regional Adjustment of Render Rate

GRAPHICS SYSTEM WITH ADDITIONAL CONTEXT

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

SYSTEMS, METHODS, AND APPPARATUS FOR MATRIX MOVE

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM

SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS

DYNAMIC MEMORY RECONFIGURATION

MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT

SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS

SYSTEMS AND METHODS TO STORE A TILE REGISTER PAIR TO MEMORY

SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MUL...

SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION...

SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILE...

SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILE...

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...

INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES

Regional Adjustment of Render Rate