Eric Ford Dellinger

Person

Boulder, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic adjustment of floating point exponent bias for exponent com...
- Patent number 12,307,217
- Issue date May 20, 2025
- Xilinx, Inc.
- Eric F. Dellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lossless compression using subnormal floating point values
- Patent number 11,824,564
- Issue date Nov 21, 2023
- Xilinx, Inc.
- Philip B. James-Roxby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting floating point data into integer data using a dynamicall...
- Patent number 11,216,275
- Issue date Jan 4, 2022
- Xilinx, Inc.
- Philip B. James-Roxby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic block (CLB) internal routing architecture for en...
- Patent number 10,715,149
- Issue date Jul 14, 2020
- Xilinx, Inc.
- Eric F. Dellinger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System-level interconnect ring for a programmable integrated circuit
- Patent number 10,042,806
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed multi-die routing in a multi-chip module
- Patent number 9,859,896
- Issue date Jan 2, 2018
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Modular array defined by standard cell logic
- Patent number 8,504,950
- Issue date Aug 6, 2013
- Otrsotech, Limited Liability Company
- Eric Dellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular array defined by standard cell logic
- Patent number 7,770,144
- Issue date Aug 3, 2010
- Eric Dellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ASIC customization with predefined via mask
- Patent number 7,648,912
- Issue date Jan 19, 2010
- Eric Dellinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ASIC customization with predefined via mask
- Patent number 7,102,237
- Issue date Sep 5, 2006
- Lightspeed Semiconductor Corporation
- Eric Dellinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ASIC routing architecture
- Patent number 6,885,043
- Issue date Apr 26, 2005
- Lightspeed Semiconductor Corporation
- Lyle Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Function block architecture with variable drive strengths
- Patent number 6,696,856
- Issue date Feb 24, 2004
- Lightspeed Semiconductor Corporation
- Lyle Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
ASIC routing architecture with variable number of custom masks
- Patent number 6,613,611
- Issue date Sep 2, 2003
- Lightspeed Semiconductor Corporation
- Dana How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hetergeneous method for determining module placement in FPGAs
- Patent number 6,457,164
- Issue date Sep 24, 2002
- Xilinx, Inc.
- L. James Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Context-sensitive self implementing modules
- Patent number 6,292,925
- Issue date Sep 18, 2001
- Xilinx, Inc.
- Eric F. Dellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for specifying routing in a logic module by direct module co...
- Patent number 6,260,182
- Issue date Jul 10, 2001
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous method for determining module placement in FPGAs
- Patent number 6,243,851
- Issue date Jun 5, 2001
- Xilinx, Inc.
- L. James Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for constraining circuit element positions in structured lay...
- Patent number 6,237,129
- Issue date May 22, 2001
- Xilinx, Inc.
- Cameron D. Patterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA modules parameterized by expressions
- Patent number 6,216,258
- Issue date Apr 10, 2001
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for generating a programming bitstream including...
- Patent number 6,205,574
- Issue date Mar 20, 2001
- Xilinx, Inc.
- Eric F. Dellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency driven layout and method for field programmable gate arrays
- Patent number 5,659,484
- Issue date Aug 19, 1997
- Xilinx, Inc.
- David Wayne Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency driven layout system and method for field programmable ga...
- Patent number 5,648,913
- Issue date Jul 15, 1997
- Xilinx, Inc.
- David Wayne Bennett
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FINE-TUNING OF NEURAL NETWORKS
- Publication number 20250190813
- Publication date Jun 12, 2025
- Adam H. Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECLAMATION OF MEMORY ECC BITS FOR ERROR TOLERANT NUMBER FORMATS
- Publication number 20250077329
- Publication date Mar 6, 2025
- Xilinx, Inc.
- Zachary BLAIR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING LOW PRECISION AND SPARSITY INFERENCE WITHOUT RETRAINING
- Publication number 20240211762
- Publication date Jun 27, 2024
- ADVANCED MICRO DEVICES, INC.
- Adam H. Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLIER BLOCK FOR BLOCK FLOATING POINT AND FLOATING POINT VALUES
- Publication number 20240118868
- Publication date Apr 11, 2024
- Xilinx, Inc.
- Philip Bryn James-Roxby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-LEVEL INTERCONNECT RING FOR A PROGRAMMABLE INTEGRATED CIRCUIT
- Publication number 20170220508
- Publication date Aug 3, 2017
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR ARRAY DEFINED BY STANDARD CELL LOGIC
- Publication number 20100299648
- Publication date Nov 25, 2010
- Eric Dellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular array defined by standard cell logic
- Publication number 20040243966
- Publication date Dec 2, 2004
- Eric Dellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASIC routing architecture
- Publication number 20030155587
- Publication date Aug 21, 2003
- Lyle Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and media for utilizing symbolic expressions in circuit mod...
- Publication number 20010001881
- Publication date May 24, 2001
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING

Eric Ford Dellinger

Person

Patents Grantslast 30 patents

Dynamic adjustment of floating point exponent bias for exponent com...

Lossless compression using subnormal floating point values

Converting floating point data into integer data using a dynamicall...

Configurable logic block (CLB) internal routing architecture for en...

System-level interconnect ring for a programmable integrated circuit

Distributed multi-die routing in a multi-chip module

Modular array defined by standard cell logic

Modular array defined by standard cell logic

ASIC customization with predefined via mask

ASIC customization with predefined via mask

ASIC routing architecture

Function block architecture with variable drive strengths

ASIC routing architecture with variable number of custom masks

Hetergeneous method for determining module placement in FPGAs

Context-sensitive self implementing modules

Method for specifying routing in a logic module by direct module co...

Heterogeneous method for determining module placement in FPGAs

Method for constraining circuit element positions in structured lay...

FPGA modules parameterized by expressions

Method and system for generating a programming bitstream including...

Frequency driven layout and method for field programmable gate arrays

Frequency driven layout system and method for field programmable ga...

Patents Applicationslast 30 patents

FINE-TUNING OF NEURAL NETWORKS

RECLAMATION OF MEMORY ECC BITS FOR ERROR TOLERANT NUMBER FORMATS

OPTIMIZING LOW PRECISION AND SPARSITY INFERENCE WITHOUT RETRAINING

MULTIPLIER BLOCK FOR BLOCK FLOATING POINT AND FLOATING POINT VALUES

SYSTEM-LEVEL INTERCONNECT RING FOR A PROGRAMMABLE INTEGRATED CIRCUIT

MODULAR ARRAY DEFINED BY STANDARD CELL LOGIC

Modular array defined by standard cell logic

ASIC routing architecture

Methods and media for utilizing symbolic expressions in circuit mod...