Eric M. Nequist

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
3D chip with shared clock distribution network
- Patent number 12,142,528
- Issue date Nov 12, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D chip with shared clock distribution network
- Patent number 11,557,516
- Issue date Jan 17, 2023
- Adeia Semiconductor Inc.
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for inter-die block level design
- Patent number 11,157,670
- Issue date Oct 26, 2021
- Xcelsis Corporation
- Javier A Delacruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Face-to-face mounted IC dies with orthogonal top interconnect layers
- Patent number 10,892,252
- Issue date Jan 12, 2021
- Xcelsis Corporation
- Eric M. Nequist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D chip sharing power circuit
- Patent number 10,672,663
- Issue date Jun 2, 2020
- Xcelsis Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for inter-die block level design
- Patent number 10,664,564
- Issue date May 26, 2020
- Xcelsis Corporation
- Javier A Delacruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D chip sharing clock interconnect layer
- Patent number 10,586,786
- Issue date Mar 10, 2020
- Xcelsis Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Face-to-face mounted IC dies with orthogonal top interconnect layers
- Patent number 10,580,757
- Issue date Mar 3, 2020
- Xcelsis Corporation
- Eric M. Nequist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mechanism and method to implement a reader mechanism for a containe...
- Patent number 8,717,182
- Issue date May 6, 2014
- Solbrae, Inc.
- Richard Vaughn Brashears
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and mechanism for implementing extraction for an integrated...
- Patent number 8,635,574
- Issue date Jan 21, 2014
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for identifying and tracking shape connectivity
- Patent number 8,631,363
- Issue date Jan 14, 2014
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing efficient locking to facilitate...
- Patent number 8,438,512
- Issue date May 7, 2013
- Cadence Design Systems, Inc.
- David Cross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for model-based routing of an integrated circuit
- Patent number 8,392,864
- Issue date Mar 5, 2013
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and computer program product for improved electrica...
- Patent number 8,386,975
- Issue date Feb 26, 2013
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for implementing extraction for an integrated...
- Patent number 8,375,342
- Issue date Feb 12, 2013
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for implementing extraction for an integrated...
- Patent number 8,316,331
- Issue date Nov 20, 2012
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for identifying and tracking shape connectivity
- Patent number 8,136,060
- Issue date Mar 13, 2012
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for identifying and tracking shape connectivity
- Patent number 8,069,426
- Issue date Nov 29, 2011
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing efficient locking to facilitate...
- Patent number 8,010,917
- Issue date Aug 30, 2011
- Cadence Design Systems, Inc.
- David Cross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing partial reconfiguration and rip-...
- Patent number 7,971,173
- Issue date Jun 28, 2011
- Cadence Design Systems, Inc.
- Richard Brashears
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for performing clearance-based zoning
- Patent number 7,904,862
- Issue date Mar 8, 2011
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for implementing extraction for an integrated...
- Patent number 7,870,517
- Issue date Jan 11, 2011
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for model-based routing of an integrated circuit
- Patent number 7,861,203
- Issue date Dec 28, 2010
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for layout optimization using model-based verific...
- Patent number 7,725,845
- Issue date May 25, 2010
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing edge optimization on an integrat...
- Patent number 7,721,235
- Issue date May 18, 2010
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for model-based design and layout of an integrate...
- Patent number 7,698,666
- Issue date Apr 13, 2010
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for identifying and tracking shape connectivity
- Patent number 7,665,045
- Issue date Feb 16, 2010
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing routing refinement and timing co...
- Patent number 7,657,860
- Issue date Feb 2, 2010
- Cadence Design Systems, Inc.
- Richard Brashears
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Representation, configuration, and reconfiguration of routing metho...
- Patent number 7,614,028
- Issue date Nov 3, 2009
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing layout, placement, and routing w...
- Patent number 7,590,955
- Issue date Sep 15, 2009
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK
- Publication number 20230137580
- Publication date May 4, 2023
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK
- Publication number 20210104436
- Publication date Apr 8, 2021
- Xcelsis Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR INTER-DIE BLOCK LEVEL DESIGN
- Publication number 20200356714
- Publication date Nov 12, 2020
- Xcelsis Corporation
- Javier A DELACRUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers
- Publication number 20200203318
- Publication date Jun 25, 2020
- Xcelsis Corporation
- Eric M. Nequist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Systems and methods for inter-die block level design
- Publication number 20190392104
- Publication date Dec 26, 2019
- Xcelsis Corporation
- Javier A DELACRUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D Chip Sharing Clock Interconnect Layer
- Publication number 20180350775
- Publication date Dec 6, 2018
- Xcelsis Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D Chip Sharing Power Circuit
- Publication number 20180330993
- Publication date Nov 15, 2018
- Xcelsis Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers
- Publication number 20180331072
- Publication date Nov 15, 2018
- Xcelsis Corporation
- Eric M. Nequist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY
- Publication number 20120131524
- Publication date May 24, 2012
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE...
- Publication number 20110314432
- Publication date Dec 22, 2011
- Cadence Design Systems, Inc.
- David Cross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR MODEL-BASED ROUTING OF AN INTEGRATED CIRCUIT
- Publication number 20110093826
- Publication date Apr 21, 2011
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPROVED ELECTRICA...
- Publication number 20090199139
- Publication date Aug 6, 2009
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND MECHANISM FOR PERFORMING CLEARANCE-BASED ZONING
- Publication number 20090172625
- Publication date Jul 2, 2009
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE...
- Publication number 20090172623
- Publication date Jul 2, 2009
- Cadence Design Systems, Inc.
- David Cross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY
- Publication number 20090089720
- Publication date Apr 2, 2009
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for model-based design and layout of an integrate...
- Publication number 20080163134
- Publication date Jul 3, 2008
- Cadence Design Systems, Inc.
- Eric Nequist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Model-Based Routing of an Integrated Circuit
- Publication number 20080163150
- Publication date Jul 3, 2008
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING

Eric M. Nequist

Person

Patents Grantslast 30 patents

3D chip with shared clock distribution network

3D chip with shared clock distribution network

Systems and methods for inter-die block level design

Face-to-face mounted IC dies with orthogonal top interconnect layers

3D chip sharing power circuit

Systems and methods for inter-die block level design

3D chip sharing clock interconnect layer

Face-to-face mounted IC dies with orthogonal top interconnect layers

Mechanism and method to implement a reader mechanism for a containe...

Method and mechanism for implementing extraction for an integrated...

Method and mechanism for identifying and tracking shape connectivity

Method and system for implementing efficient locking to facilitate...

Method and system for model-based routing of an integrated circuit

Method, system, and computer program product for improved electrica...

Method and mechanism for implementing extraction for an integrated...

Method and mechanism for implementing extraction for an integrated...

Method and mechanism for identifying and tracking shape connectivity

Method and mechanism for identifying and tracking shape connectivity

Method and system for implementing efficient locking to facilitate...

Method and system for implementing partial reconfiguration and rip-...

Method and mechanism for performing clearance-based zoning

Method and mechanism for implementing extraction for an integrated...

Method and system for model-based routing of an integrated circuit

System and method for layout optimization using model-based verific...

Method and system for implementing edge optimization on an integrat...

Method and system for model-based design and layout of an integrate...

Method and mechanism for identifying and tracking shape connectivity

Method and system for implementing routing refinement and timing co...

Representation, configuration, and reconfiguration of routing metho...

Method and system for implementing layout, placement, and routing w...

Patents Applicationslast 30 patents

3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK

3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK

SYSTEMS AND METHODS FOR INTER-DIE BLOCK LEVEL DESIGN

Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers

Systems and methods for inter-die block level design

3D Chip Sharing Clock Interconnect Layer

3D Chip Sharing Power Circuit

Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers

METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY

METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE...

METHOD AND SYSTEM FOR MODEL-BASED ROUTING OF AN INTEGRATED CIRCUIT

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPROVED ELECTRICA...

METHOD AND MECHANISM FOR PERFORMING CLEARANCE-BASED ZONING

METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE...

METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY

Method and system for model-based design and layout of an integrate...

Method and System for Model-Based Routing of an Integrated Circuit