Erin A. Handgen

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single and double chip spare
- Patent number 11,030,061
- Issue date Jun 8, 2021
- Hewlett Packard Enterprise Development LP
- Gary Gostin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying accessibility based on memory access patterns
- Patent number 10,585,598
- Issue date Mar 10, 2020
- Hewlett Packard Enterprise Development LP
- Andrew Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM row sparing
- Patent number 10,468,118
- Issue date Nov 5, 2019
- Hewlett Packard Enterprise Development LP
- Andrew C. Walton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single and double chip space
- Patent number 10,379,971
- Issue date Aug 13, 2019
- Hewlett Packard Enterprise Development LP
- Gary Gostin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory erasure information in cache lines
- Patent number 9,778,982
- Issue date Oct 3, 2017
- Hewlett Packard Enterprise Development LP
- Lidia Warnes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single and double chip spare
- Patent number 9,690,673
- Issue date Jun 27, 2017
- Gary Gostin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory control systems with directory caches and methods for operat...
- Patent number 8,244,983
- Issue date Aug 14, 2012
- Hewlett-Packard Development Company, L.P.
- Erin A. Handgen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for achieving enhanced memory access capabilities
- Patent number 7,818,508
- Issue date Oct 19, 2010
- Hewlett-Packard Development Company, L.P.
- Bryan Hornung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directory caches, and methods for operation thereof
- Patent number 7,624,234
- Issue date Nov 24, 2009
- Hewlett-Packard Development Company, L.P.
- Erin A. Handgen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with a scalable high-bandwidth architecture
- Patent number 7,343,440
- Issue date Mar 11, 2008
- Hewlett-Packard Development Company, L.P.
- Erin Antony Handgen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for optimizing pre-fetch memory transactions
- Patent number 6,901,486
- Issue date May 31, 2005
- Hewlett-Packard Development Company, L.P.
- Erin Antony Handgen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer graphics system utilizing parallel processing for enhanced...
- Patent number 5,821,950
- Issue date Oct 13, 1998
- Hewlett-Packard Company
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sorting apparatus having plurality of registers with associated mul...
- Patent number 5,222,243
- Issue date Jun 22, 1993
- Hewlett-Packard Company
- Randall D. Briggs
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SINGLE AND DOUBLE CHIP SPARE
- Publication number 20190354447
- Publication date Nov 21, 2019
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Gary Gostin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODIFYING ACCESIBILITY BASED ON MEMORY ACCESS PATTERNS
- Publication number 20190102091
- Publication date Apr 4, 2019
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Andrew Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE AND DOUBLE CHIP SPARE
- Publication number 20170255531
- Publication date Sep 7, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Gary Gostin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ROW SPARING
- Publication number 20170169905
- Publication date Jun 15, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Andrew C. Walton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ERASURE INFORMATION IN CACHE LINES
- Publication number 20160274968
- Publication date Sep 22, 2016
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Lidia WARNES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE AND DOUBLE CHIP SPARE
- Publication number 20150006977
- Publication date Jan 1, 2015
- Gary Gostin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Achieving Enhanced Memory Access Capabilities
- Publication number 20080270743
- Publication date Oct 30, 2008
- Bryan Hornung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROL SYSTEMS WITH DIRECTORY CACHES AND METHODS FOR OPERAT...
- Publication number 20080104331
- Publication date May 1, 2008
- Erin A. HANDGEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Directory caches, and methods for operation thereof
- Publication number 20080059710
- Publication date Mar 6, 2008
- Erin A. Handgen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit with a scalable high-bandwidth architecture
- Publication number 20050080958
- Publication date Apr 14, 2005
- Erin Antony Handgen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for optimizing pre-fetch memory transactions
- Publication number 20040006671
- Publication date Jan 8, 2004
- Erin Antony Handgen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read data storage controller with bypass read data return path
- Publication number 20030172235
- Publication date Sep 11, 2003
- George Thomas Letey
- G06 - COMPUTING CALCULATING COUNTING

Erin A. Handgen

Person

Patents Grantslast 30 patents

Single and double chip spare

Modifying accessibility based on memory access patterns

DRAM row sparing

Single and double chip space

Memory erasure information in cache lines

Single and double chip spare

Memory control systems with directory caches and methods for operat...

System and method for achieving enhanced memory access capabilities

Directory caches, and methods for operation thereof

Integrated circuit with a scalable high-bandwidth architecture

Method and system for optimizing pre-fetch memory transactions

Computer graphics system utilizing parallel processing for enhanced...

Sorting apparatus having plurality of registers with associated mul...

Patents Applicationslast 30 patents

SINGLE AND DOUBLE CHIP SPARE

MODIFYING ACCESIBILITY BASED ON MEMORY ACCESS PATTERNS

SINGLE AND DOUBLE CHIP SPARE

DRAM ROW SPARING

MEMORY ERASURE INFORMATION IN CACHE LINES

SINGLE AND DOUBLE CHIP SPARE

System and Method for Achieving Enhanced Memory Access Capabilities

MEMORY CONTROL SYSTEMS WITH DIRECTORY CACHES AND METHODS FOR OPERAT...

Directory caches, and methods for operation thereof

Integrated circuit with a scalable high-bandwidth architecture

Method and system for optimizing pre-fetch memory transactions

Read data storage controller with bypass read data return path