Fabrice Letertre

Person

Grenoble, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Pseudo-substrate with improved efficiency of usage of single crysta...
- Patent number 12,112,976
- Issue date Oct 8, 2024
- Soitec
- Fabrice Letertre
- C30 - CRYSTAL GROWTH
Information Patent Grant
Pseudo-substrate with improved efficiency of usage of single crysta...
- Patent number 10,910,256
- Issue date Feb 2, 2021
- SOITEC
- Fabrice Letertre
- B32 - LAYERED PRODUCTS
Information Patent Grant
Integrated circuit formed from a stack of two series-connected chips
- Patent number 10,672,746
- Issue date Jun 2, 2020
- Exagan
- Domenico Lo Verde
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of substrates with a useful layer of monocrystalline se...
- Patent number 10,002,763
- Issue date Jun 19, 2018
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxation and transfer of strained material layers
- Patent number 9,041,165
- Issue date May 26, 2015
- Soitec
- Fabrice Letertre
- C30 - CRYSTAL GROWTH
Information Patent Grant
Substrate cutting device and method
- Patent number 8,991,673
- Issue date Mar 31, 2015
- Soitec
- Olivier Rayssac
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Grant
Process for fabricating a semiconductor structure employing a tempo...
- Patent number 8,951,887
- Issue date Feb 10, 2015
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterostructure for electronic power components, optoelectronic or...
- Patent number 8,759,881
- Issue date Jun 24, 2014
- Soitec
- Jean-Marc Bethoux
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Manufacturing process for a stacked structure comprising a thin lay...
- Patent number 8,679,946
- Issue date Mar 25, 2014
- Commissariat a l'Energie Atomique et aux Energies Alternatives
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strain engineered composite semiconductor substrates and methods of...
- Patent number 8,679,942
- Issue date Mar 25, 2014
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optoelectronic substrate and methods of making same
- Patent number 8,541,290
- Issue date Sep 24, 2013
- Soitec
- Fabrice Letertre
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fabrication of substrates with a useful layer of monocrystalline se...
- Patent number 8,507,361
- Issue date Aug 13, 2013
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for relaxation and transfer of strained layers and structur...
- Patent number 8,492,244
- Issue date Jul 23, 2013
- Soitec
- Pascal Guenard
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Semiconductor structures and devices including semiconductor materi...
- Patent number 8,487,295
- Issue date Jul 16, 2013
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming relaxed layers of semiconductor materials, semic...
- Patent number 8,486,771
- Issue date Jul 16, 2013
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing process for a stacked structure comprising a thin lay...
- Patent number 8,481,409
- Issue date Jul 9, 2013
- Commissariat a l'Energie Atomique
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxation of strained layers
- Patent number 8,481,408
- Issue date Jul 9, 2013
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of fabricating semiconductor structures and devices with st...
- Patent number 8,461,014
- Issue date Jun 11, 2013
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having an InGaN layer
- Patent number 8,343,782
- Issue date Jan 1, 2013
- Soitec
- Fabrice M. Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of substrates with a useful layer of monocrystalline se...
- Patent number 8,252,664
- Issue date Aug 28, 2012
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating an epitaxially grown layer
- Patent number 8,216,368
- Issue date Jul 10, 2012
- Soitec
- Bruce Faure
- C30 - CRYSTAL GROWTH
Information Patent Grant
Process for fabricating a structure for epitaxy without an exclusio...
- Patent number 8,154,022
- Issue date Apr 10, 2012
- Soitec
- Chantal Arena
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Methods of fabricating semiconductor structures and devices using g...
- Patent number 8,114,754
- Issue date Feb 14, 2012
- S.O.I. Tec Silicon on Insulator Technologies
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming an assembly for transfer of a useful layer usin...
- Patent number 8,093,687
- Issue date Jan 10, 2012
- S.O.I. Tec Silicon on Insulator Technologies
- Fabrice Letertre
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Substrate cutting device and method
- Patent number 8,083,115
- Issue date Dec 27, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Olivier Rayssac
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Grant
Methods and structures for relaxation of strained layers
- Patent number 8,048,693
- Issue date Nov 1, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Fabrice Letertre
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Methods for relaxation and transfer of strained layers and structur...
- Patent number 7,981,767
- Issue date Jul 19, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Pascal Guenard
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Transfer method with a treatment of a surface to be bonded
- Patent number 7,972,939
- Issue date Jul 5, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Sébastien Kerdiles
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for making substrates and substrates formed therefrom
- Patent number 7,939,428
- Issue date May 10, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Alice Boussagol
- C30 - CRYSTAL GROWTH
Information Patent Grant
Process for fabricating a structure for epitaxy without an exclusio...
- Patent number 7,902,045
- Issue date Mar 8, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Chantal Arena
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTA...
- Publication number 20210050248
- Publication date Feb 18, 2021
- SOITEC
- Fabrice Letertre
- C30 - CRYSTAL GROWTH
Information Patent Application
INTEGRATED CIRCUIT FORMED FROM A STACK OF TWO SERIES-CONNECTED CHIPS
- Publication number 20190378823
- Publication date Dec 12, 2019
- Exagan
- Domenico Lo Verde
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTA...
- Publication number 20150243549
- Publication date Aug 27, 2015
- SOITEC
- Fabrice Letertre
- C30 - CRYSTAL GROWTH
Information Patent Application
MANUFACTURING PROCESS FOR A STACKED STRUCTURE COMPRISING A THIN LAY...
- Publication number 20130230967
- Publication date Sep 5, 2013
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING AN InGaN LAYER
- Publication number 20130058369
- Publication date Mar 7, 2013
- SOITEC
- Fabrice M. Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FABRICATING A SEMICONDUCTOR STRUCTURE EMPLOYING A TEMPO...
- Publication number 20120329243
- Publication date Dec 27, 2012
- SOITEC
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR...
- Publication number 20120241821
- Publication date Sep 27, 2012
- SOITEC
- Jean-Marc Bethoux
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELAXATION OF STRAINED LAYERS
- Publication number 20120214291
- Publication date Aug 23, 2012
- SOITEC
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING SEMICONDUCTOR MATERI...
- Publication number 20120112205
- Publication date May 10, 2012
- SOITEC
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES WITH ST...
- Publication number 20120100692
- Publication date Apr 26, 2012
- SOITEC
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SE...
- Publication number 20120058621
- Publication date Mar 8, 2012
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE CUTTING DEVICE AND METHOD
- Publication number 20120048906
- Publication date Mar 1, 2012
- Olivier Rayssac
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Application
FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SE...
- Publication number 20120012048
- Publication date Jan 19, 2012
- S.O.I.Tec Silicon on Insulator Technologies
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELAXATION AND TRANSFER OF STRAINED MATERIAL LAYERS
- Publication number 20110291247
- Publication date Dec 1, 2011
- S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
- Fabrice Letertre
- C30 - CRYSTAL GROWTH
Information Patent Application
OPTOELECTRONIC SUBSTRATE AND METHODS OF MAKING SAME
- Publication number 20110237008
- Publication date Sep 29, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Fabrice Letertre
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHODS FOR RELAXATION AND TRANSFER OF STRAINED LAYERS AND STRUCTUR...
- Publication number 20110180911
- Publication date Jul 28, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Pascal Guenard
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SE...
- Publication number 20110171812
- Publication date Jul 14, 2011
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELAXATION OF STRAINED LAYERS
- Publication number 20110143522
- Publication date Jun 16, 2011
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING AN InGaN LAYER
- Publication number 20110134954
- Publication date Jun 9, 2011
- Fabrice M. Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR...
- Publication number 20110127581
- Publication date Jun 2, 2011
- Jean-Marc Bethoux
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES USING G...
- Publication number 20110114965
- Publication date May 19, 2011
- S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSIO...
- Publication number 20110037075
- Publication date Feb 17, 2011
- Chantal Arena
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR MAKING SUBSTRATES AND SUBSTRATES FORMED THEREFROM
- Publication number 20110039368
- Publication date Feb 17, 2011
- Alice Boussagol
- C30 - CRYSTAL GROWTH
Information Patent Application
METHODS OF FORMING RELAXED LAYERS OF SEMICONDUCTOR MATERIALS, SEMIC...
- Publication number 20100176490
- Publication date Jul 15, 2010
- Fabrice LETERTRE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAIN ENGINEERED COMPOSITE SEMICONDUCTOR SUBSTRATES AND METHODS OF...
- Publication number 20100127353
- Publication date May 27, 2010
- S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
- Fabrice LETERTRE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR RELAXATION AND TRANSFER OF STRAINED LAYERS AND STRUCTUR...
- Publication number 20100032793
- Publication date Feb 11, 2010
- Pascal Guenard
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHODS AND STRUCTURES FOR RELAXATION OF STRAINED LAYERS
- Publication number 20100032805
- Publication date Feb 11, 2010
- Fabrice LETERTRE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSFER METHOD WITH A TREATMENT OF A SURFACE TO BE BONDED
- Publication number 20100015780
- Publication date Jan 21, 2010
- S.O.I.Tec Silicon on Insulator Technologies
- Sébastien KERDILES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILAYER STRUCTURE AND FABRICATION THEREOF
- Publication number 20100006857
- Publication date Jan 14, 2010
- S. O. I. Tec Silicon on Insulator Technologies
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING AN EPITAXIALLY GROWN LAYER
- Publication number 20090321884
- Publication date Dec 31, 2009
- S.O.I.Tec Silicon on Insulator Technologies
- Bruce Faure
- C30 - CRYSTAL GROWTH

Fabrice Letertre

Person

Patents Grantslast 30 patents

Pseudo-substrate with improved efficiency of usage of single crysta...

Pseudo-substrate with improved efficiency of usage of single crysta...

Integrated circuit formed from a stack of two series-connected chips

Fabrication of substrates with a useful layer of monocrystalline se...

Relaxation and transfer of strained material layers

Substrate cutting device and method

Process for fabricating a semiconductor structure employing a tempo...

Heterostructure for electronic power components, optoelectronic or...

Manufacturing process for a stacked structure comprising a thin lay...

Strain engineered composite semiconductor substrates and methods of...

Optoelectronic substrate and methods of making same

Fabrication of substrates with a useful layer of monocrystalline se...

Methods for relaxation and transfer of strained layers and structur...

Semiconductor structures and devices including semiconductor materi...

Methods of forming relaxed layers of semiconductor materials, semic...

Manufacturing process for a stacked structure comprising a thin lay...

Relaxation of strained layers

Methods of fabricating semiconductor structures and devices with st...

Semiconductor device having an InGaN layer

Fabrication of substrates with a useful layer of monocrystalline se...

Method of fabricating an epitaxially grown layer

Process for fabricating a structure for epitaxy without an exclusio...

Methods of fabricating semiconductor structures and devices using g...

Methods for forming an assembly for transfer of a useful layer usin...

Substrate cutting device and method

Methods and structures for relaxation of strained layers

Methods for relaxation and transfer of strained layers and structur...

Transfer method with a treatment of a surface to be bonded

Methods for making substrates and substrates formed therefrom

Process for fabricating a structure for epitaxy without an exclusio...

Patents Applicationslast 30 patents

PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTA...

INTEGRATED CIRCUIT FORMED FROM A STACK OF TWO SERIES-CONNECTED CHIPS

PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTA...

MANUFACTURING PROCESS FOR A STACKED STRUCTURE COMPRISING A THIN LAY...

SEMICONDUCTOR DEVICE HAVING AN InGaN LAYER

PROCESS FOR FABRICATING A SEMICONDUCTOR STRUCTURE EMPLOYING A TEMPO...

HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR...

RELAXATION OF STRAINED LAYERS

SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING SEMICONDUCTOR MATERI...

METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES WITH ST...

FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SE...

SUBSTRATE CUTTING DEVICE AND METHOD

FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SE...

RELAXATION AND TRANSFER OF STRAINED MATERIAL LAYERS

OPTOELECTRONIC SUBSTRATE AND METHODS OF MAKING SAME

METHODS FOR RELAXATION AND TRANSFER OF STRAINED LAYERS AND STRUCTUR...

FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SE...

RELAXATION OF STRAINED LAYERS

SEMICONDUCTOR DEVICE HAVING AN InGaN LAYER

HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR...

METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES USING G...

PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSIO...

METHODS FOR MAKING SUBSTRATES AND SUBSTRATES FORMED THEREFROM

METHODS OF FORMING RELAXED LAYERS OF SEMICONDUCTOR MATERIALS, SEMIC...

STRAIN ENGINEERED COMPOSITE SEMICONDUCTOR SUBSTRATES AND METHODS OF...

METHODS FOR RELAXATION AND TRANSFER OF STRAINED LAYERS AND STRUCTUR...

METHODS AND STRUCTURES FOR RELAXATION OF STRAINED LAYERS

TRANSFER METHOD WITH A TREATMENT OF A SURFACE TO BE BONDED

MULTILAYER STRUCTURE AND FABRICATION THEREOF

METHOD OF FABRICATING AN EPITAXIALLY GROWN LAYER