FARAN NOURI

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
NMOS transistor devices and methods for fabricating same
- Patent number 8,330,225
- Issue date Dec 11, 2012
- Applied Materials, Inc.
- Sunderraj Thirupapuliyur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming a transistor and modulating channel stress
- Patent number 8,105,908
- Issue date Jan 31, 2012
- Applied Materials, Inc.
- Sunderraj Thirupapuliyur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
NMOS transistor devices and methods for fabricating same
- Patent number 7,994,015
- Issue date Aug 9, 2011
- Applied Materials, Inc.
- Sunderraj Thirupapuliyur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming a transistor
- Patent number 7,968,413
- Issue date Jun 28, 2011
- Applied Materials, Inc.
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming a transistor
- Patent number 7,833,869
- Issue date Nov 16, 2010
- Applied Materials, Inc.
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for contact resistance reduction of advanced CMOS devices
- Patent number 7,795,124
- Issue date Sep 14, 2010
- Applied Materials, Inc.
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a silicon oxynitride layer
- Patent number 7,569,502
- Issue date Aug 4, 2009
- Applied Materials, Inc.
- Christopher Olsen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming a transistor
- Patent number 7,413,957
- Issue date Aug 19, 2008
- Applied Materials, Inc.
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for suppressing narrow width effects in CMOS technology
- Patent number 6,313,011
- Issue date Nov 6, 2001
- KoninKlijke Philips Electronics N.V. (KPENV)
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing shallow source/drain junctions in a salicid...
- Patent number 6,274,445
- Issue date Aug 14, 2001
- Philips Semi-Conductor, Inc.
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of an insulating spacer to prevent threshold voltage roll-off i...
- Patent number 6,251,747
- Issue date Jun 26, 2001
- Philips Semiconductors, Inc.
- Tammy Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming isolation areas with improved isolation oxide
- Patent number 6,235,609
- Issue date May 22, 2001
- Philips Electronics North America Corp.
- Samit Sengupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for eliminating stress induced dislocations in CMOS devices
- Patent number 6,221,735
- Issue date Apr 24, 2001
- Philips Semiconductors, Inc.
- Martin Manley
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME
- Publication number 20110278651
- Publication date Nov 17, 2011
- Sunderraj Thirupapuliyur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME
- Publication number 20100264470
- Publication date Oct 21, 2010
- Applied Materials, Inc.
- SUNDERRAJ THIRUPAPULIYUR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING A TRANSISTOR
- Publication number 20080299735
- Publication date Dec 4, 2008
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING A TRANSISTOR
- Publication number 20080280413
- Publication date Nov 13, 2008
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR CONTACT RESISTANCE REDUCTION OF ADVANCED CMOS DEVICES
- Publication number 20070298575
- Publication date Dec 27, 2007
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS
- Publication number 20070287244
- Publication date Dec 13, 2007
- APPLIED MATERIALS, INC., A Delaware corporation
- Meihua Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS
- Publication number 20070284668
- Publication date Dec 13, 2007
- APPLIED MATERIALS, INC., A Delaware corporation
- Meihua Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SILICON OXYNITRIDE LAYER
- Publication number 20070087583
- Publication date Apr 19, 2007
- APPLIED MATERIALS, INC.
- Christopher Olsen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming a transistor and creating channel stress
- Publication number 20060289900
- Publication date Dec 28, 2006
- APPLIED MATERIALS, INC.
- Sunderraj Thirupapuliyur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon nitride film with stress control
- Publication number 20060009041
- Publication date Jan 12, 2006
- R. Suryanarayanan Iyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming a transistor
- Publication number 20050287752
- Publication date Dec 29, 2005
- APPLIED MATERIALS, INC.
- Faran Nouri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a silicon oxynitride layer
- Publication number 20050130448
- Publication date Jun 16, 2005
- APPLIED MATERIALS, INC.
- Christopher Olsen
- H01 - BASIC ELECTRIC ELEMENTS

FARAN NOURI

Person

Patents Grantslast 30 patents

NMOS transistor devices and methods for fabricating same

Methods for forming a transistor and modulating channel stress

NMOS transistor devices and methods for fabricating same

Methods for forming a transistor

Methods for forming a transistor

Methods for contact resistance reduction of advanced CMOS devices

Method of forming a silicon oxynitride layer

Methods for forming a transistor

Method for suppressing narrow width effects in CMOS technology

Method of manufacturing shallow source/drain junctions in a salicid...

Use of an insulating spacer to prevent threshold voltage roll-off i...

Method for forming isolation areas with improved isolation oxide

Method for eliminating stress induced dislocations in CMOS devices

Patents Applicationslast 30 patents

NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME

NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME

METHODS FOR FORMING A TRANSISTOR

METHODS FOR FORMING A TRANSISTOR

METHODS FOR CONTACT RESISTANCE REDUCTION OF ADVANCED CMOS DEVICES

ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS

CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS

METHOD OF FORMING A SILICON OXYNITRIDE LAYER

Methods for forming a transistor and creating channel stress

Silicon nitride film with stress control

Methods for forming a transistor

Method of forming a silicon oxynitride layer