Fei-Sheng Hsu

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Computer-aided design system to automate scan synthesis at register...
- Patent number 8,543,950
- Issue date Sep 24, 2013
- Syntest Technologies, Inc.
- Laung-Terng (L.-T.) Wang
- G01 - MEASURING TESTING
Information Patent Grant
Event-driven emulation system
- Patent number 7,970,597
- Issue date Jun 28, 2011
- Springsoft, Inc.
- Meng-Chyi Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-capture DFT system for scan-based integrated circuits
- Patent number 7,904,773
- Issue date Mar 8, 2011
- Syntest Technologies, Inc.
- Laung-Terng (L. T.) Wang
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for shifting at-speed scan patterns in a scan-...
- Patent number 7,512,851
- Issue date Mar 31, 2009
- Syntest Technologies, Inc.
- Laung-Terng Wang
- G01 - MEASURING TESTING
Information Patent Grant
Computer-aided design system to automate scan synthesis at register...
- Patent number 7,331,032
- Issue date Feb 12, 2008
- Syntest Technologies, Inc.
- Laung-Terng (L. -T.) Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer-aided design system to automate scan synthesis at register...
- Patent number 6,957,403
- Issue date Oct 18, 2005
- Syntest Technologies, Inc.
- Laung-Terng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-capture DFT system for scan-based integrated circuits
- Patent number 6,954,887
- Issue date Oct 11, 2005
- Syntest Technologies, Inc.
- Laung-Terng (L.-T.) Wang
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...
- Publication number 20120246604
- Publication date Sep 27, 2012
- Syntest Technologies, Inc.
- Laung-Terng (L. -T.) WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT-DRIVEN EMULATION SYSTEM
- Publication number 20090287468
- Publication date Nov 19, 2009
- SPRINGSOFT, INC.
- Meng-Chyi Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple-Capture DFT system for scan-based integrated circuits
- Publication number 20090070646
- Publication date Mar 12, 2009
- Syntest Technologies, Inc.
- Laung-Terng (L.T.) Wang
- G01 - MEASURING TESTING
Information Patent Application
Multiple-capture DFT system for scan-based integrated circuits
- Publication number 20050235186
- Publication date Oct 20, 2005
- Syntest Technologies, Inc.
- Laung-Terng Wang
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for shifting at-speed scan patterns in a scan-...
- Publication number 20050055617
- Publication date Mar 10, 2005
- Laung-Terng Wang
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for testing asynchronous set/reset faults in a...
- Publication number 20040153926
- Publication date Aug 5, 2004
- Khader S. Abdel-Hafez
- G01 - MEASURING TESTING
Information Patent Application
Computer-aided design system to automate scan synthesis at register...
- Publication number 20030023941
- Publication date Jan 30, 2003
- Laung-Terng (L.-T.) Wang
- G01 - MEASURING TESTING
Information Patent Application
Multiple-capture DFT system for scan-based integrated circuits
- Publication number 20020184560
- Publication date Dec 5, 2002
- Laung-Terng Wang
- G01 - MEASURING TESTING

Fei-Sheng Hsu

Person

Patents Grantslast 30 patents

Computer-aided design system to automate scan synthesis at register...

Event-driven emulation system

Multiple-capture DFT system for scan-based integrated circuits

Method and apparatus for shifting at-speed scan patterns in a scan-...

Computer-aided design system to automate scan synthesis at register...

Computer-aided design system to automate scan synthesis at register...

Multiple-capture DFT system for scan-based integrated circuits

Patents Applicationslast 30 patents

COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...

EVENT-DRIVEN EMULATION SYSTEM

Multiple-Capture DFT system for scan-based integrated circuits

Multiple-capture DFT system for scan-based integrated circuits

Method and apparatus for shifting at-speed scan patterns in a scan-...

Method and apparatus for testing asynchronous set/reset faults in a...

Computer-aided design system to automate scan synthesis at register...

Multiple-capture DFT system for scan-based integrated circuits