Claims
- 1. A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells; said method comprising the steps of:
(a) shifting in N pseudorandom stimuli or predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during the shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation; (c) shifting out N output responses of all said scan cells for analysis during the shift-out operation; and (d) repeating the steps of (a)-(c) until a predetermined limiting criteria is reached, wherein (a) and (c) occur substantially concurrently.
- 2. The method of claim 1, wherein each said capture clock is programmable to contain one or more clock pulses for performing said shift-in, said shift-out, and said capture operations on all said scan cells within one said clock domain; wherein said clock domain is solely controlled by said capture clock; and said capture clock can be selectively generated internally or controlled externally, and can operate selectively at its rated clock speed (at-speed) or at a selected clock speed.
- 3. The method of claim 1, further comprising providing N scan enable (SE) signals each within one said clock domain; wherein said SE signals are used to switch said shift-in, said shift-out, and said capture operations; and further said SE signals can be selectively generated internally or controlled externally, and are operated selectively at the rated clock speeds (at-speed) or at selected clock speeds.
- 4. The method of claim 3, wherein said SE signals are used to switch said shift-in, said shift-out, and said capture operations further comprises selectively controlling said shift clock pulses within one said clock domain, when one said capture clock controlling said clock domain contains one or more said shift clock pulses, during each said capture operation.
- 5. The method of claim 3, wherein said providing N scan enable (SE) signals further comprises selectively using one or more global scan enable (GSE) signals to drive a plurality of said scan enable (SE) signals, when said clock domains controlled by said a plurality of said SE signals each does not contain any said shift clock pulses during each said capture operation; wherein said GSE signal is operated at a selected reduced clock speed.
- 6. The method of claim 1, wherein said shifting in N pseudorandom stimuli or predetermined stimuli further comprises operating all capture clocks at selected clock speeds or at the same clock speed, and when operated at the same clock speed, all said capture clocks are selectively skewed so that at any given time only scan cells within one said clock domain are changing states to reduce power consumption.
- 7. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises performing said capture operation concurrently on a plurality of clock domains which do not have any logic block crossing each other.
- 8. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises applying said capture clocks in a selected order for detecting or locating additional faults in said integrated circuit or circuit assembly.
- 9. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises applying another ordered sequence of capture clocks selectively longer or shorter than said ordered sequence of capture clocks for detecting or locating additional faults in said integrated circuit or circuit assembly.
- 10. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises disabling one or more capture clocks to facilitate fault diagnosis.
- 11. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises selectively operating said capture clock at a selected clock speed for detecting or locating stuck-at faults within the clock domain controlled by said capture clock.
- 12. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises selectively operating said capture clock at its rated clock speed for detecting or locating delay faults within the clock domain controlled by said capture clock.
- 13. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises selectively reducing said capture clock speed to the level where delay faults associated with all multiple-cycle paths of equal cycle latency within the clock domain are tested at a predetermined rated clock speed.
- 14. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises selectively operating two said capture clocks at selected clock speeds for detecting or locating stuck-at faults crossing two said clock domains.
- 15. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises selectively adjusting the relative clock delay of two said capture clocks operating at selected clock speeds for detecting or locating delay faults crossing two said clock domains.
- 16. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises selectively adjusting the relative clock delay of two said capture clocks to the level where delay faults associated with all multiple-cycle paths of equal cycle latency crossing two said clock domains are tested at a predetermined rated clock speed.
- 17. The method of claim 1, wherein said applying an ordered sequence of capture clocks further comprises controlling the relative clock delay between any two adjacent capture clocks internally or external to said integrated circuit or circuit assembly.
- 18. The method of claim 1, providing an automatic test equipment (ATE) and wherein said shifting out N output responses of all said scan cells for analysis during the shift-out operation further comprises selectively comparing said N output responses directly with their expected output responses in said ATE.
- 19. The method of claim 1, wherein said shifting out N output responses of all said scan cells for analysis during the shift-out operation further comprises selectively compacting said N output responses to signatures using a compact operation.
- 20. The method of claim 19, providing an automatic test equipment (ATE) and wherein said compacting said N output responses to signatures further comprises comparing said signatures with their expected signatures after said predetermined limiting criteria is reached; wherein said comparing said signatures with their expected signatures further comprises comparing said signatures inside said integrated circuit or shifting out said signatures for comparison in said ATE.
- 21. The method of claim 1, wherein said scan cells are multiplexed D flip-flops or level sensitive latches, and further wherein said integrated circuit or circuit assembly under test is a full-scan or partial-scan design.
- 22. The method of claim 1, wherein said faults further comprise stuck-at faults and delay faults; wherein said stuck-at faults further comprises other stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, and wherein said delay faults further comprises other non-stuck-type delay faults, including transition (gate-delay), multiple-cycle delay, and path-delay faults.
- 23. An apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells; said apparatus comprising:
(a) first hardware for shifting in N pseudorandom stimuli or predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during the shift-in operation; (b) second hardware for applying an ordered sequence of capture clocks to all said scan cells within said N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation; (c) third hardware for shifting out N output responses of all said scan cells for analysis during the shift-out operation; and (d) fourth hardware for repeating the steps of (a)-(c) until a predetermined limiting criteria is reached, wherein (a) and (c) occur substantially concurrently.
- 24. The apparatus of claim 23, further comprising fifth hardware for indicating errors after said predetermined limiting criteria is reached.
- 25. The apparatus of claim 23, wherein each said capture clock is programmable to contain one or more clock pulses for performing said shift-in, said shift-out, and said capture operations on all said scan cells within one said clock domain; wherein said clock domain is solely controlled by said capture clock; and said capture clock can be selectively generated internally or controlled externally, and can operate selectively at its rated clock speed (at-speed) or at a selected clock speed.
- 26. The apparatus of claim 23, providing an automatic test equipment (ATE) and wherein said first hardware for shifting in N pseudorandom stimuli or predetermined stimuli to all said scan cells further comprises further hardware for generating and shifting in said N pseudorandom stimuli or predetermined stimuli to all said scan cells within said integrated circuit, within said circuit assembly, or in said ATE.
- 27. The apparatus of claim 23, wherein said second hardware for applying an ordered sequence of capture clocks further comprises further hardware for generating said ordered sequence; wherein said ordered sequence includes one or more said shift clock pulses in one or more capture clocks during each said capture operation.
- 28. The apparatus of claim 23, providing an automatic test equipment (ATE) and wherein said third hardware for shifting out N output responses of all said scan cells for analysis during the shift-out operation further comprises further hardware for selectively comparing said N output responses directly with their expected output responses in said ATE.
- 29. The apparatus of claim 23, wherein said third hardware for shifting out N output responses of all said scan cells for analysis during the shift-out operation further comprises further hardware for selectively compacting said N output responses to signatures using a compact operation.
- 30. The apparatus of claim 29, providing an automatic test equipment (ATE) and wherein said compacting said N output responses to signatures further comprises further hardware for comparing said signatures with their expected signatures after said predetermined limiting criteria is reached; wherein said comparing said signatures with their expected signatures further comprises further hardware for comparing said signatures inside said integrated circuit or shifting out said signatures for comparison in said ATE.
- 31. The apparatus of claim 23, wherein said scan cells are multiplexed D flip-flops or level sensitive latches, and further wherein said integrated circuit or circuit assembly under test is a full-scan or partial-scan design.
- 32. The apparatus of claim 23, wherein said faults further comprise stuck-at faults and delay faults; wherein said stuck-at faults further comprises other stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, and wherein said delay faults further comprises other non-stuck-type delay faults, including transition (gate-delay), multiple-cycle delay, and path-delay faults.
- 33. The apparatus of claim 23, wherein said hardware of (a)-(d) are selectively placed inside or external to said integrated circuit or circuit assembly.
- 34. A computer-aided design (CAD) method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test mode, where N>1; said CAD method comprising the computer-implemented steps of:
(a) compiling the HDL (hardware description language) code or netlist that represents said integrated circuit or circuit assembly in physical form into a design database; (b) performing self-test rule check for checking whether said design database contains any multiple-capture self-test rule violations; (c) performing self-test rule repair until all said multiple-capture self-test rule violations have been fixed; (d) performing multiple-capture self-test synthesis for generating a self-test HDL code or netlist; and (e) generating HDL test benches and ATE (automatic test equipment) test programs, where one or more capture clocks must contain one or more shift clock pulses during a selected capture operation, for verifying the correctness of said self-test HDL code or netlist.
- 35. The CAD method of claim 34, including adapting said steps of (a)-(e) to accept user-supplied self-test control information and report the results and errors, if any.
- 36. The CAD method of claim 34, wherein said performing self-test rule check further comprises determining the number of clock domains and capture clocks required for self-test, the clock domains to be tested concurrently, the ordered sequence of capture clocks to be applied for self-test, and the capture clocks to be operated selectively at the rated clock speeds or at selected clock speeds.
- 37. The CAD method of claim 34, wherein said performing self-test rule repair further comprises selectively using a scan enable (SE) signal or a test enable (TE) signal to repair said self-test rule violations on selected asynchronous set/reset flip-flops, selected tri-state busses, and selected low-power gated-clock flip-flops or latches in selected clock domains.
- 38. The CAD method of claim 34, wherein said multiple-capture self-test synthesis further comprises inserting spare scan cells into selected clock domains.
- 39. The CAD method of claim 34, wherein said generating HDL test benches and ATE test programs further comprises the steps of transforming said design database into an equivalent combinational circuit model based on said ordered sequence of capture clocks, and performing combinational fault simulation to compute the circuit's output responses, signatures, and fault coverage.
- 40. The CAD method of claim 34, wherein said faults further comprise stuck-at faults and delay faults; wherein said stuck-at faults further comprises other stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, and wherein said delay faults further comprises other non-stuck-type delay faults, including transition (gate-delay), multiple-cycle delay, and path-delay faults.
- 41. A computer-aided design (CAD) method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test mode, where N>1; said CAD method comprising the computer-implemented steps of:
(a) compiling the HDL (hardware description language) code or netlist that represents said integrated circuit or circuit assembly in physical form into a design database; (b) performing scan rule check for checking whether said design database contains any multiple-capture scan rule violations; (c) performing scan rule repair until all said multiple-capture scan rule violations have been fixed; (d) performing multiple-capture scan synthesis for generating a scan HDL netlist; and (e) generating HDL test benches and ATE (automatic test equipment) test programs, where one or more capture clocks must contain one or more shift clock pulses during a selected capture operation, for verifying the correctness of said scan HDL netlist.
- 42. The CAD method of claim 41, including adapting said steps of (a)-(e) to accept user-supplied scan control information and report the results and errors, if any.
- 43. The CAD method of claim 41, wherein said performing scan rule check further comprises determining the number of clock domains and capture clocks required for scan-test, the clock domains to be tested concurrently, the ordered sequence of capture clocks to be applied for scan-test, and the capture clocks to be operated selectively at the rated clock speeds or at selected clock speeds.
- 44. The CAD method of claim 41, wherein said performing scan rule repair further comprises selectively using a scan enable (SE) signal or a test enable (TE) signal to repair said scan rule violations on selected asynchronous set/reset flip-flops, selected tri-state busses, and selected low-power gated-clock flip-flops or latches in selected clock domains.
- 45. The CAD method of claim 41, wherein said performing multiple-capture scan synthesis further comprises inserting spare scan cells into selected clock domains.
- 46. The CAD method of claim 41, wherein said generating HDL test benches and ATE test programs further comprises the steps of transforming said design database into an equivalent combinational circuit model based on said ordered sequence of capture clocks, and performing combinational ATPG (automatic test pattern generation) to generate the circuit's test patterns and report its fault coverage.
- 47. The CAD method of claim 41, wherein said generating HDL test benches and ATE test programs further comprises performing combinational logic simulation on said combinational circuit model to compute said circuit's signatures when a compact operation is employed to compact said circuit's output responses.
- 48. The CAD method of claim 41, wherein said faults further comprise stuck-at faults and delay faults; wherein said stuck-at faults further comprises other stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, and wherein said delay faults further comprises other non-stuck-type delay faults, including transition (gate-delay), multiple-cycle delay, and path-delay faults.
- 49. A computer-aided design (CAD) method for generating pseudorandom stimuli and predetermined stimuli to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain having one capture clock and a plurality of scan cells; said CAD method comprising the computer implemented steps of:
(a) compiling the scan-based HDL (hardware description language) code or netlist that represents said scan-based integrated circuit or circuit assembly in physical form into a design database; (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks; (c) transforming said design database into an equivalent combinational circuit model according to said optimal ordered sequence of capture clocks; (d) generating said pseudorandom stimuli and said predetermined stimuli for detecting or locating said faults; and (e) translating said pseudorandom stimuli and said predetermined stimuli to HDL test benches and ATE (automatic test equipment) test program for verifying the correctness of said scan-based HDL code or netlist representing said scan-based integrated circuit or circuit assembly.
- 50. The CAD method of claim 49, including adapting said steps of (a)-(f) to accept user-supplied scan-based control information and report the results and errors, if any.
- 51. The CAD method of claim 49, wherein said (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks further comprises the computer implemented steps of:
(f) receiving input constraints from an external source, said input constraints further comprising a list of capture clocks to be ordered; (g) based on said input constraints, analyzing said design database which selected clock domains do not interact with each other, and when said selected clock domains do not interact with each other, selectively replacing said capture clocks controlling said selected clock domains with one or more grouped capture clocks each for testing a plurality of said selected clock domains at the same frequency concurrently; and (h) based on said input constraints and said grouped capture clocks, further analyzing said design database to search for said optimal ordered sequence of capture clocks using the least amount or near-minimal amount of computer memory when transforming said design database into said equivalent combinational circuit model.
- 52. The CAD method of claim 49, wherein said (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks further comprises selectively specifying said optimal ordered sequence of capture clocks in overlapping or non-overlapping mode.
- 53. The CAD method of claim 49, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises duplicating said design database as many time frames as needed according to said optimal ordered sequence of capture clocks; wherein said duplicating said design database as many time frames as needed further comprises removing or pruning constant logic tied to logic value 0, 1, unknown (X) or high-impedance (Z), uncontrollable logic, unobservable logic, and uncontrollable/unobservable logic from said design database.
- 54. The CAD method of claim 49, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises transforming each selected lower-powered gated-clock flip-flop or latch into its equivalent non-gated-clock flip-flop or latch model, respectively.
- 55. The CAD method of claim 49, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises transforming a selected scan cell into its equivalent transparent flip-flop or latch model when said selected scan cell receives shift clock pulses slower than its previous scan cell or faster than its next scan cell within the same scan chain in each said clock domain during the shift-in, or shift-out operation.
- 56. The CAD method of claim 49, wherein said (d) generating said pseudorandom stimuli and said predetermined stimuli further comprises performing combinational fault simulation for generating a selected number of said pseudorandom stimuli in said self-test mode or said scan-test mode.
- 57. The CAD method of claim 49, wherein said (d) generating said pseudorandom stimuli and said predetermined stimuli further comprises performing combinational ATPG (automatic test pattern generation) for generating said predetermined stimuli in said scan-test mode.
- 58. The CAD method of claim 57, wherein said performing combinational ATPG further comprises generating race-free scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing asynchronous set/reset flip-flops whose set/reset pins are not always disabled during the capture operation.
- 59. The CAD method of claim 58, wherein said containing asynchronous set/reset flip-flops whose set/reset pins are not always disabled during the capture operation further comprises using a scan enable (SE) signal to control said asynchronous set/reset flip-flops during said capture operation.
- 60. The CAD method of claim 57, wherein said performing combinational ATPG further comprises generating contention-free scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing tri-state busses which are not always disabled during the capture operation.
- 61. The CAD method of claim 60, wherein said containing tri-state busses which are not always disabled during the capture operation further comprises using a scan enable (SE) signal and said input constraints to control said tri-state busses during said capture operation.
- 62. The CAD method of claim 57, wherein said performing combinational ATPG further comprises generating low-power scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing low-power gated-clock flip-flops or latches whose gated clocks are not always enabled during the capture operation.
- 63. The CAD method of claim 62, wherein said containing low-power gated-clock flip-flops or latches whose gated clocks are not always enabled during the capture operation further comprises using a scan enable (SE) signal to control said low-power gated-clock flip-flops or latches during said capture operation.
- 64. The CAD method of claim 49, wherein said (e) translating said pseudorandom stimuli and said predetermined stimuli to HDL test benches and ATE (automatic test equipment) test programs further comprises specifying multiple-phased timing diagrams, in selected overlapping or non-overlapping mode, according to said optimal ordered sequence of capture clocks.
- 65. The CAD method of claim 49, wherein said faults further comprise stuck-at faults and delay faults; wherein said stuck-at faults further comprises other stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, and wherein said delay faults further comprises other non-stuck-type delay faults, including transition (gate-delay), multiple-cycle delay, and path-delay faults.
- 66. A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a computer-aided design (CAD) method for generating pseudorandom stimuli and predetermined stimuli to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain having one capture clock and a plurality of scan cells; said CAD method comprising the computer implemented steps of:
(a) compiling the scan-based HDL (hardware description language) code or netlist that represents said scan-based integrated circuit or circuit assembly in physical form into a design database; (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks; (c) transforming said design database into an equivalent combinational circuit model according to said optimal ordered sequence of capture clocks; (d) generating said pseudorandom stimuli and said predetermined stimuli for detecting or locating said faults; and (e) translating said pseudorandom stimuli and said predetermined stimuli to HDL test benches and ATE (automatic test equipment) test program for verifying the correctness of said scan-based HDL code or netlist representing said scan-based integrated circuit or circuit assembly.
- 67. The computer-readable memory of claim 66, including adapting said steps of (a)-(f) to accept user-supplied scan-based control information and report the results and errors, if any.
- 68. The computer-readable memory of claim 66, wherein said (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks further comprises the computer implemented steps of:
(f) receiving input constraints from an external source, said input constraints further comprising a list of capture clocks to be ordered; (g) based on said input constraints, analyzing said design database which selected clock domains do not interact with each other, and when said selected clock domains do not interact with each other, selectively replacing said capture clocks controlling said selected clock domains with one or more grouped capture clocks each for testing a plurality of said selected clock domains at the same frequency concurrently; and (h) based on said input constraints and said grouped capture clocks, further analyzing said design database to search for said optimal ordered sequence of capture clocks using the least amount or near-minimal amount of computer memory when transforming said design database into said equivalent combinational circuit model.
- 69. The computer-readable memory of claim 66, wherein said (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks further comprises selectively specifying said optimal ordered sequence of capture clocks in overlapping or non-overlapping mode.
- 70. The computer-readable memory of claim 66, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises duplicating said design database as many time frames as needed according to said optimal ordered sequence of capture clocks; wherein said duplicating said design database as many time frames as needed further comprises removing or pruning constant logic tied to logic value 0, 1, unknown (X) or high-impedance (Z), uncontrollable logic, unobservable logic, and uncontrollable/unobservable logic from said design database.
- 71. The computer-readable memory of claim 66, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises transforming each selected lower-powered gated-clock flip-flop or latch into its equivalent non-gated-clock flip-flop or latch model, respectively.
- 72. The computer-readable memory of claim 66, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises transforming a selected scan cell into its equivalent transparent flip-flop or latch model when said selected scan cell receives shift clock pulses slower than its previous scan cell or faster than its next scan cell within the same scan chain in each said clock domain during the shift-in, or shift-out operation.
- 73. The computer-readable memory of claim 66, wherein said (d) generating said pseudorandom stimuli and said predetermined stimuli further comprises performing combinational fault simulation for generating a selected number of said pseudorandom stimuli in said self-test mode or said scan-test mode.
- 74. The computer-readable memory of claim 66, wherein said (d) generating said pseudorandom stimuli and said predetermined stimuli further comprises performing combinational ATPG (automatic test pattern generation) for generating said predetermined stimuli in said scan-test mode.
- 75. The computer-readable memory of claim 74, wherein said performing combinational ATPG further comprises generating race-free scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing asynchronous set/reset flip-flops whose set/reset pins are not always disabled during the capture operation.
- 76. The computer-readable memory of claim 75, wherein said containing asynchronous set/reset flip-flops whose set/reset pins are not always disabled during the capture operation further comprises using a scan enable (SE) signal to control said asynchronous set/reset flip-flops during said capture operation.
- 77. The computer-readable memory of claim 74, wherein said performing combinational ATPG further comprises generating contention-free scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing tri-state busses which are not always disabled during the capture operation.
- 78. The computer-readable memory of claim 77, wherein said containing tri-state busses which are not always disabled during the capture operation further comprises using a scan enable (SE) signal and said input constraints to control said tri-state busses during said capture operation.
- 79. The computer-readable memory of claim 74, wherein said performing combinational ATPG further comprises generating low-power scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing low-power gated-clock flip-flops or latches whose gated clocks are not always enabled during the capture operation.
- 80. The computer-readable memory of claim 79, wherein said containing low-power gated-clock flip-flops or latches whose gated clocks are not always enabled during the capture operation further comprises using a scan enable (SE) signal to control said low-power gated-clock flip-flops or latches during said capture operation.
- 81. The computer-readable memory of claim 66, wherein said (e) translating said pseudorandom stimuli and said predetermined stimuli to HDL test benches and ATE (automatic test equipment) test programs further comprises specifying multiple-phased timing diagrams, in selected overlapping or non-overlapping mode, according to said optimal ordered sequence of capture clocks.
- 82. The computer-readable memory of claim 66, wherein said faults further comprise stuck-at faults and delay faults; wherein said stuck-at faults further comprises other stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, and wherein said delay faults further comprises other non-stuck-type delay faults, including transition (gate-delay), multiple-cycle delay, and path-delay faults.
- 83. An electronic design automation system comprising:
a processor; a bus coupled to said processor; and a computer-readable memory coupled to said bus and having computer-readable program code stored therein for causing said electronic design automation system to perform a computer-aided design (CAD) method for generating pseudorandom stimuli and predetermined stimuli to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain having one capture clock and a plurality of scan cells; said CAD method comprising the computer implemented steps of:
(a) compiling the scan-based HDL (hardware description language) code or netlist that represents said scan-based integrated circuit or circuit assembly in physical form into a design database; (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks; (c) transforming said design database into an equivalent combinational circuit model according to said optimal ordered sequence of capture clocks; (d) generating said pseudorandom stimuli and said predetermined stimuli for detecting or locating said faults; and (e) translating said pseudorandom stimuli and said predetermined stimuli to HDL test benches and ATE (automatic test equipment) test program for verifying the correctness of said scan-based HDL code or netlist representing said scan-based integrated circuit or circuit assembly.
- 84. The system of claim 83, including adapting said steps of (a)-(f) to accept user-supplied scan-based control information and report the results and errors, if any.
- 85. The system of claim 83, wherein said (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks further comprises the computer implemented steps of:
(f) receiving input constraints from an external source, said input constraints further comprising a list of capture clocks to be ordered; (g) based on said input constraints, analyzing said design database which selected clock domains do not interact with each other, and when said selected clock domains do not interact with each other, selectively replacing said capture clocks controlling said selected clock domains with one or more grouped capture clocks each for testing a plurality of said selected clock domains at the same frequency concurrently; and (h) based on said input constraints and said grouped capture clocks, further analyzing said design database to search for said optimal ordered sequence of capture clocks using the least amount or near-minimal amount of computer memory when transforming said design database into said equivalent combinational circuit model.
- 86. The system of claim 83, wherein said (b) performing clock-domain analysis for generating an optimal ordered sequence of capture clocks further comprises selectively specifying said optimal ordered sequence of capture clocks in overlapping or non-overlapping mode.
- 87. The system of claim 83, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises duplicating said design database as many time frames as needed according to said optimal ordered sequence of capture clocks; wherein said duplicating said design database as many time frames as needed further comprises removing or pruning constant logic tied to logic value 0, 1, unknown (X) or high-impedance (Z), uncontrollable logic, unobservable logic, and uncontrollable/unobservable logic from said design database.
- 88. The system of claim 83, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises transforming each selected lower-powered gated-clock flip-flop or latch into its equivalent non-gated-clock flip-flop or latch model, respectively.
- 89. The system of claim 83, wherein said (c) transforming said design database into an equivalent combinational circuit model further comprises transforming a selected scan cell into its equivalent transparent flip-flop or latch model when said selected scan cell receives shift clock pulses slower than its previous scan cell or faster than its next scan cell within the same scan chain in each said clock domain during the shift-in, or shift-out operation.
- 90. The system of claim 83, wherein said (d) generating said pseudorandom stimuli and said predetermined stimuli further comprises performing combinational fault simulation for generating a selected number of said pseudorandom stimuli in said self-test mode or said scan-test mode.
- 91. The system of claim 83, wherein said (d) generating said pseudorandom stimuli and said predetermined stimuli further comprises performing combinational ATPG (automatic test pattern generation) for generating said predetermined stimuli in said scan-test mode.
- 92. The system of claim 91, wherein said performing combinational ATPG further comprises generating race-free scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing asynchronous set/reset flip-flops whose set/reset pins are not always disabled during the capture operation.
- 93. The system of claim 92, wherein said containing asynchronous set/reset flip-flops whose set/reset pins are not always disabled during the capture operation further comprises using a scan enable (SE) signal to control said asynchronous set/reset flip-flops during said capture operation.
- 94. The system of claim 91, wherein said performing combinational ATPG further comprises generating contention-free scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing tri-state busses which are not always disabled during the capture operation.
- 95. The system of claim 94, wherein said containing tri-state busses which are not always disabled during the capture operation further comprises using a scan enable (SE) signal and said input constraints to control said tri-state busses during said capture operation.
- 96. The system of claim 91, wherein said performing combinational ATPG further comprises generating low-power scan patterns (said predetermined stimuli) to test said scan-based integrated circuit or circuit assembly containing low-power gated-clock flip-flops or latches whose gated clocks are not always enabled during the capture operation.
- 97. The system of claim 96, wherein said containing low-power gated-clock flip-flops or latches whose gated clocks are not always enabled during the capture operation further comprises using a scan enable (SE) signal to control said low-power gated-clock flip-flops or latches during said capture operation.
- 98. The system of claim 83, wherein said (e) translating said pseudorandom stimuli and said predetermined stimuli to HDL test benches and ATE (automatic test equipment) test programs further comprises specifying multiple-phased timing diagrams, in selected overlapping or non-overlapping mode, according to said optimal ordered sequence of capture clocks.
- 99. The system of claim 83, wherein said faults further comprise stuck-at faults and delay faults; wherein said stuck-at faults further comprises other stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, and wherein said delay faults further comprises other non-stuck-type delay faults, including transition (gate-delay), multiple-cycle delay, and path-delay faults.
- 100. An apparatus for generating pseudorandom stimuli or predetermined stimuli to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain having one capture clock and a plurality of shift-in, shift-out, and capture operations; said apparatus comprising:
(a) first hardware for using a scan enable (SE) signal to disable selected asynchronous set/reset flip-flops or latches during each said shift-in or said shift-out operation, and selectively enable or disable said selected asynchronous set/reset flip-flops or latches during each said capture operation, in selected said clock domains; (b) second hardware for using a scan enable (SE) signal to disable selected tri-state busses during each said shift-in or said shift-out operation, and selectively enable or disable said selected tri-state busses during each said capture operation, in selected said clock domains; and (c) third hardware for using a scan enable (SE) signal to enable selected low-power gated-clock flip-flops or latches during each said shift-in or said shift-out operation, and selectively enable or disable said selected low-power gated-clock flip-flops or latches during each said capture operation, in selected said clock domains.
RELATED APPLICATION DATA
[0001] This application claims the benefit of U.S. Provisional Application No. 60/277,654 filed Mar. 22, 2001, titled “Multiple-Capture Scan Design and Test Generation System for Scan-Based Integrated Circuits”, which is hereby incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60277654 |
Mar 2001 |
US |