Feroze P. Taraporevala

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual-box location aware and dual-bitmap voltage domain aware on-chi...
- Patent number 8,713,501
- Issue date Apr 29, 2014
- Synopsys, Inc.
- Jiayong Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient data compression for vector-based static timing analysis
- Patent number 8,666,722
- Issue date Mar 4, 2014
- Synopsys, Inc.
- Jinfeng Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Simultaneous multi-corner static timing analysis using samples-base...
- Patent number 8,615,727
- Issue date Dec 24, 2013
- Synopsys, Inc.
- Praveen Ghanta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-power-domain static timing analysis
- Patent number 8,321,824
- Issue date Nov 27, 2012
- Synopsys, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating variation-aware library data with efficient device misma...
- Patent number 8,204,730
- Issue date Jun 19, 2012
- Synopsys, Inc.
- Jinfeng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing sequential cells using interdependent setup and hold...
- Patent number 7,774,731
- Issue date Aug 10, 2010
- Synopsys, Inc.
- Ali Dasdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing sequential cells using interdependent setup and hold...
- Patent number 7,506,293
- Issue date Mar 17, 2009
- Synopsys, Inc.
- Ali Dasdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,961,916
- Issue date Nov 1, 2005
- Synopsys, Inc.
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,442,743
- Issue date Aug 27, 2002
- Monterey Design Systems
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrent placement of gates and associated...
- Patent number 6,385,760
- Issue date May 7, 2002
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design optimization using logical and physical information
- Patent number 6,286,128
- Issue date Sep 4, 2001
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Simultaneous Multi-Corner Static Timing Analysis Using Samples-Base...
- Publication number 20120159414
- Publication date Jun 21, 2012
- Synopsys, Inc.
- Praveen Ghanta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Data Compression For Vector-Based Static Timing Analysis
- Publication number 20110307226
- Publication date Dec 15, 2011
- Synopsys, Inc.
- Jinfeng Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE-POWER-DOMAIN STATIC TIMING ANALYSIS
- Publication number 20100281444
- Publication date Nov 4, 2010
- Synopsys, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating Variation-Aware Library Data With Efficient Device Misma...
- Publication number 20090306953
- Publication date Dec 10, 2009
- Synopsys, Inc.
- Jinfeng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Characterizing Sequential Cells Using Interdependent Setup And Hold...
- Publication number 20080295053
- Publication date Nov 27, 2008
- Synopsys, Inc.
- Ali Dasdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Characterizing sequential cells using interdependent setup and hold...
- Publication number 20070226668
- Publication date Sep 27, 2007
- Synopsys, Inc.
- Ali Dasdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement method for integrated circuit design using topo-clustering
- Publication number 20020138816
- Publication date Sep 26, 2002
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED...
- Publication number 20010047507
- Publication date Nov 29, 2001
- LAWRENCE PILEGGI
- G06 - COMPUTING CALCULATING COUNTING

Feroze P. Taraporevala

Person

Patents Grantslast 30 patents

Dual-box location aware and dual-bitmap voltage domain aware on-chi...

Efficient data compression for vector-based static timing analysis

Simultaneous multi-corner static timing analysis using samples-base...

Multiple-power-domain static timing analysis

Generating variation-aware library data with efficient device misma...

Characterizing sequential cells using interdependent setup and hold...

Characterizing sequential cells using interdependent setup and hold...

Placement method for integrated circuit design using topo-clustering

Placement method for integrated circuit design using topo-clustering

System and method for concurrent placement of gates and associated...

Method for design optimization using logical and physical information

Patents Applicationslast 30 patents

Simultaneous Multi-Corner Static Timing Analysis Using Samples-Base...

Efficient Data Compression For Vector-Based Static Timing Analysis

MULTIPLE-POWER-DOMAIN STATIC TIMING ANALYSIS

Generating Variation-Aware Library Data With Efficient Device Misma...

Characterizing Sequential Cells Using Interdependent Setup And Hold...

Characterizing sequential cells using interdependent setup and hold...

Placement method for integrated circuit design using topo-clustering

SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED...