Francis BENISTANT

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Device with diffusion blocking layer in source/drain region
- Patent number 10,164,099
- Issue date Dec 25, 2018
- GLOBALFOUNDRIES Inc.
- Shesh Mani Pandey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple-step epitaxial growth S/D regions for NMOS FinFET
- Patent number 9,966,433
- Issue date May 8, 2018
- GLOBALFOUNDRIES Inc.
- Zhiqing Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device with diffusion blocking layer in source/drain region
- Patent number 9,947,788
- Issue date Apr 17, 2018
- GLOBALFOUNDRIES Inc.
- Shesh Mani Pandey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extended drain metal-oxide-semiconductor transistor
- Patent number 9,871,132
- Issue date Jan 16, 2018
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Kun Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation scheme for high voltage device
- Patent number 9,673,084
- Issue date Jun 6, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Kun Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET conformal junction and high epi surface dopant concentration...
- Patent number 9,577,040
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES Inc.
- Peijie Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET conformal junction and abrupt junction with reduced damage m...
- Patent number 9,559,176
- Issue date Jan 31, 2017
- GLOBALFOUNDRIES Inc.
- Peijie Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET conformal junction and high EPI surface dopant concentration...
- Patent number 9,406,752
- Issue date Aug 2, 2016
- GLOBALFOUNDRIES Inc.
- Peijie Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET conformal junction and abrupt junction with reduced damage m...
- Patent number 9,397,162
- Issue date Jul 19, 2016
- Globalfoundries Inc.
- Peijie Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with double doped drain transistor
- Patent number 9,269,770
- Issue date Feb 23, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and methods of forming the semiconductor devi...
- Patent number 8,994,107
- Issue date Mar 31, 2015
- GLOBALFOUNDRIES, INC.
- El Mehdi Bazizi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus to reduce thermal variations within an integra...
- Patent number 8,860,142
- Issue date Oct 14, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor devices with reduced junction...
- Patent number 8,354,321
- Issue date Jan 15, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus to reduce thermal variations within an integra...
- Patent number 8,293,544
- Issue date Oct 23, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor devices with reduced junction...
- Patent number 8,053,340
- Issue date Nov 8, 2011
- National University of Singapore
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modified source/drain re-oxidation method and system
- Patent number 7,271,435
- Issue date Sep 18, 2007
- Micron Technology, Inc.
- Paul J. Rudeck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow low energy ion implantation into pad oxide for improving th...
- Patent number 7,259,072
- Issue date Aug 21, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of activating polysilicon gate structure dopants after offse...
- Patent number 6,969,646
- Issue date Nov 29, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION
- Publication number 20180175198
- Publication date Jun 21, 2018
- GLOBALFOUNDRIES INC.
- Shesh Mani Pandey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE-STEP EPITAXIAL GROWTH S/D REGIONS FOR NMOS FINFET
- Publication number 20180040696
- Publication date Feb 8, 2018
- GLOBALFOUNDRIES INC.
- Zhiqing LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A DOPED REGION IN A FIN USING A VARIABLE THICKNE...
- Publication number 20170288041
- Publication date Oct 5, 2017
- GLOBALFOUNDRIES INC.
- Shesh Mani Pandey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION
- Publication number 20170229578
- Publication date Aug 10, 2017
- GLOBALFOUNDRIES INC.
- Shesh Mani Pandey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION...
- Publication number 20160308005
- Publication date Oct 20, 2016
- GLOBALFOUNDRIES INC.
- Peijie FENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE M...
- Publication number 20160293718
- Publication date Oct 6, 2016
- GLOBALFOUNDRIES INC.
- Peijie FENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE M...
- Publication number 20160190252
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES INC.
- Peijie FENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION...
- Publication number 20160190251
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES INC.
- Peijie FENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION SCHEME FOR HIGH VOLTAGE DEVICE
- Publication number 20160163583
- Publication date Jun 9, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Kun LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SEMICONDUCTOR DEVI...
- Publication number 20140054649
- Publication date Feb 27, 2014
- GLOBALFOUNDRIES INC.
- El Mehdi Bazizi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRA...
- Publication number 20130099321
- Publication date Apr 25, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...
- Publication number 20120034745
- Publication date Feb 9, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benjamin COLOMBEAU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus to reduce thermal variations within an integra...
- Publication number 20100019329
- Publication date Jan 28, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...
- Publication number 20090087971
- Publication date Apr 2, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Benjamin COLOMBEAU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH DOUBLE DOPED DRAIN TRANSISTOR
- Publication number 20070210376
- Publication date Sep 13, 2007
- Chartered Semiconductor Manufacturing LTD.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow low energy ion implantation into pad oxide for improving th...
- Publication number 20050239256
- Publication date Oct 27, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of activating polysilicon gate structure dopants after offse...
- Publication number 20040164320
- Publication date Aug 26, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS

Francis BENISTANT

Person

Patents Grantslast 30 patents

Device with diffusion blocking layer in source/drain region

Multiple-step epitaxial growth S/D regions for NMOS FinFET

Device with diffusion blocking layer in source/drain region

Extended drain metal-oxide-semiconductor transistor

Isolation scheme for high voltage device

FinFET conformal junction and high epi surface dopant concentration...

FinFET conformal junction and abrupt junction with reduced damage m...

FinFET conformal junction and high EPI surface dopant concentration...

FinFET conformal junction and abrupt junction with reduced damage m...

Integrated circuit system with double doped drain transistor

Semiconductor devices and methods of forming the semiconductor devi...

Method and apparatus to reduce thermal variations within an integra...

Method for fabricating semiconductor devices with reduced junction...

Method and apparatus to reduce thermal variations within an integra...

Method for fabricating semiconductor devices with reduced junction...

Modified source/drain re-oxidation method and system

Shallow low energy ion implantation into pad oxide for improving th...

Method of activating polysilicon gate structure dopants after offse...

Patents Applicationslast 30 patents

DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION

MULTIPLE-STEP EPITAXIAL GROWTH S/D REGIONS FOR NMOS FINFET

METHOD FOR FORMING A DOPED REGION IN A FIN USING A VARIABLE THICKNE...

DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION

FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION...

FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE M...

FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE M...

FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION...

ISOLATION SCHEME FOR HIGH VOLTAGE DEVICE

SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SEMICONDUCTOR DEVI...

METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRA...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...

Method and apparatus to reduce thermal variations within an integra...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...

INTEGRATED CIRCUIT SYSTEM WITH DOUBLE DOPED DRAIN TRANSISTOR

Shallow low energy ion implantation into pad oxide for improving th...

Method of activating polysilicon gate structure dopants after offse...