Frederick J. Aichelmann Jr.

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fault tolerant memory
- Patent number 5,659,678
- Issue date Aug 19, 1997
- International Business Machines Corporation
- Frederick John Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault tolerant memory
- Patent number 5,434,868
- Issue date Jul 18, 1995
- International Business Machines Corporation
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast access memory structure
- Patent number 5,276,846
- Issue date Jan 4, 1994
- International Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory organization with arrays having an alternate data port facility
- Patent number 5,166,903
- Issue date Nov 24, 1992
- International Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory organization with arrays having an alternate data port facility
- Patent number 5,150,328
- Issue date Sep 22, 1992
- Internation Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip bit reordering structure
- Patent number 4,845,664
- Issue date Jul 4, 1989
- International Business Machines Corp.
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed buffer store arrangement for quick wide transfer of data
- Patent number 4,823,259
- Issue date Apr 18, 1989
- International Business Machines Corporation
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory structure for nonsequential storage of block bytes in multi-...
- Patent number 4,796,222
- Issue date Jan 3, 1989
- International Business Machines Corporation
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ECC circuit failure detector/quick word verifier
- Patent number 4,740,968
- Issue date Apr 26, 1988
- International Business Machines Corporation
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intermediate memory array with a parallel port and a buffered seria...
- Patent number 4,718,039
- Issue date Jan 5, 1988
- International Business Machines
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction for multiple bit output chips
- Patent number 4,617,664
- Issue date Oct 14, 1986
- International Business Machines Corporation
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error logging memory system for avoiding miscorrection of triple er...
- Patent number 4,604,751
- Issue date Aug 5, 1986
- International Business Machines Corporation
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory address permutation apparatus
- Patent number 4,506,364
- Issue date Mar 19, 1985
- International Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for storing data words in fault tolerant memory to recover u...
- Patent number 4,458,349
- Issue date Jul 3, 1984
- International Business Machines Corporation
- Frederick J. Aichelmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recirculating loop memory array having a shift register buffer for...
- Patent number 4,388,701
- Issue date Jun 14, 1983
- International Business Machines Corp.
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Two speed recirculating memory system using partially good components
- Patent number 4,365,318
- Issue date Dec 21, 1982
- International Business Machines Corp.
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Recirculating loop memory array tester
- Patent number 4,363,124
- Issue date Dec 7, 1982
- International Business Machines Corp.
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Recirculating loop memory array fault locator
- Patent number 4,313,199
- Issue date Jan 26, 1982
- International Business Machines Corp.
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
LARAM Memory with reordered selection sequence for refresh
- Patent number 4,238,842
- Issue date Dec 9, 1980
- IBM Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor controlled memory refresh
- Patent number 4,172,282
- Issue date Oct 23, 1979
- International Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Bidirectional serial-parallel-serial charge-coupled device
- Patent number 4,165,539
- Issue date Aug 21, 1979
- International Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiplexed and interlaced charge-coupled serial-parallel-serial me...
- Patent number 4,152,781
- Issue date May 1, 1979
- International Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Parity checking scheme for detecting word line failure in multiple...
- Patent number 4,103,823
- Issue date Aug 1, 1978
- International Business Machines Corporation
- Frederick John Aichelmann
- G06 - COMPUTING CALCULATING COUNTING

Frederick J. Aichelmann Jr.

Person

Patents Grantslast 30 patents

Fault tolerant memory

Fault tolerant memory

Fast access memory structure

Memory organization with arrays having an alternate data port facility

Memory organization with arrays having an alternate data port facility

On-chip bit reordering structure

High speed buffer store arrangement for quick wide transfer of data

Memory structure for nonsequential storage of block bytes in multi-...

ECC circuit failure detector/quick word verifier

Intermediate memory array with a parallel port and a buffered seria...

Error correction for multiple bit output chips

Error logging memory system for avoiding miscorrection of triple er...

Memory address permutation apparatus

Method for storing data words in fault tolerant memory to recover u...

Recirculating loop memory array having a shift register buffer for...

Two speed recirculating memory system using partially good components

Recirculating loop memory array tester

Recirculating loop memory array fault locator

LARAM Memory with reordered selection sequence for refresh

Processor controlled memory refresh

Bidirectional serial-parallel-serial charge-coupled device

Multiplexed and interlaced charge-coupled serial-parallel-serial me...

Parity checking scheme for detecting word line failure in multiple...