Fumiyasu Hirose

Person

Kawasaki, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Node grouping method and data transmitting method in a network
- Patent number 6,334,156
- Issue date Dec 25, 2001
- Fujitsu Limited
- Hidetoshi Matsuoka
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data transferring buffer
- Patent number 5,740,468
- Issue date Apr 14, 1998
- Fujitsu Limited
- Fumiyasu Hirose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic instruction string generation method and device for verif...
- Patent number 5,708,594
- Issue date Jan 13, 1998
- Fujitsu Limited
- Hiroaki Iwashita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Uniform load distributing method for use in executing parallel proc...
- Patent number 5,535,387
- Issue date Jul 9, 1996
- Fujitsu Limited
- Hidetoshi Matsuoka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic simulation method
- Patent number 5,475,832
- Issue date Dec 12, 1995
- Fujitsu Limited
- Minoru Shoji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable logic operation apparatus
- Patent number 5,424,734
- Issue date Jun 13, 1995
- Fujitsu Limited
- Kioto Hirahara
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gate addressing system for logic simulation machine
- Patent number 5,245,549
- Issue date Sep 14, 1993
- Fujitsu Limited
- Minoru Shoji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate processor arrangement for simulation processor system
- Patent number 4,942,615
- Issue date Jul 17, 1990
- Fujitsu Limited
- Fumiyasu Hirose
- G06 - COMPUTING CALCULATING COUNTING

Fumiyasu Hirose

Person

Patents Grantslast 30 patents

Node grouping method and data transmitting method in a network

Data transferring buffer

Automatic instruction string generation method and device for verif...

Uniform load distributing method for use in executing parallel proc...

Logic simulation method

Variable logic operation apparatus

Gate addressing system for logic simulation machine

Gate processor arrangement for simulation processor system