Garrett S. Koch

Person

Cambridge, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple uses for BIST test latches
- Patent number 8,006,153
- Issue date Aug 23, 2011
- International Business Machines Corporation
- Steven Ross Ferguson
- G01 - MEASURING TESTING
Information Patent Grant
Multiple uses for BIST test latches
- Patent number 7,574,642
- Issue date Aug 11, 2009
- International Business Machines Corporation
- Steven Ross Ferguson
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for testing a memory
- Patent number 7,562,267
- Issue date Jul 14, 2009
- International Business Machines Corporation
- Anthony G. Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with data line steering and bitline redundancy
- Patent number 7,117,400
- Issue date Oct 3, 2006
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-dimensional redundancy calculation
- Patent number 7,003,704
- Issue date Feb 21, 2006
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Dram CAM cell with hidden refresh
- Patent number 6,430,073
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-ported memory with asynchronous and synchronous protocol
- Patent number 6,282,144
- Issue date Aug 28, 2001
- International Business Machines Corporation
- Kevin A. Batson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for real time two dimensional redundancy alloc...
- Patent number 6,026,505
- Issue date Feb 15, 2000
- International Business Machines Corporation
- Erik Leigh Hedberg
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced built-in self-test circuit and method
- Patent number 5,918,003
- Issue date Jun 29, 1999
- International Business Machines Corporation
- Garrett Stephen Koch
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for real time two dimensional redundancy alloc...
- Patent number 5,859,804
- Issue date Jan 12, 1999
- International Business Machines Corporation
- Erik Leigh Hedberg
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array built-in self test circuit for testing multi-port memo...
- Patent number 5,796,745
- Issue date Aug 18, 1998
- International Business Machines Corporation
- Robert D. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array built-in self-test circuit having a programmable patte...
- Patent number 5,790,564
- Issue date Aug 4, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Test converage of embedded memories on semiconductor substrates
- Patent number 5,784,323
- Issue date Jul 21, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array built-in self-test circuit having a programmable patte...
- Patent number 5,771,242
- Issue date Jun 23, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to determine erroneous value in memory cells u...
- Patent number 5,761,213
- Issue date Jun 2, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rapid compare of two binary numbers
- Patent number 5,745,498
- Issue date Apr 28, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using one memory to supply addresses to an associated memory during...
- Patent number 5,740,098
- Issue date Apr 14, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using one memory to supply addresses to an associated memory during...
- Patent number 5,563,833
- Issue date Oct 8, 1996
- International Business Machines Corporation
- Robert D. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
BIST tester for multiple memories
- Patent number 5,535,164
- Issue date Jul 9, 1996
- International Business Machines Corporation
- Robert D. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for real time data error capture and compressi...
- Patent number 5,317,573
- Issue date May 31, 1994
- International Business Machines Corporation
- Orest Bula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self calibrating timing circuit
- Patent number 5,093,584
- Issue date Mar 3, 1992
- International Business Machines Corporation
- Justin A. Woyke
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE USES FOR BIST TEST LATCHES
- Publication number 20080313512
- Publication date Dec 18, 2008
- Steven Ross Ferguson
- G01 - MEASURING TESTING
Information Patent Application
Multiple uses for bist test latches
- Publication number 20060242519
- Publication date Oct 26, 2006
- Steven Ross Ferguson
- G01 - MEASURING TESTING
Information Patent Application
Methods and apparatus for testing a memory
- Publication number 20060156091
- Publication date Jul 13, 2006
- International Business Machines Corporation
- Anthony G. Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device with data line steering and bitline redundancy
- Publication number 20040153899
- Publication date Aug 5, 2004
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Application
Two-dimensional redundancy calculation
- Publication number 20040093540
- Publication date May 13, 2004
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM CAM CELL WITH HIDDEN REFRESH
- Publication number 20020067632
- Publication date Jun 6, 2002
- Kevin A. Batson
- G11 - INFORMATION STORAGE

Garrett S. Koch

Person

Patents Grantslast 30 patents

Multiple uses for BIST test latches

Multiple uses for BIST test latches

Methods and apparatus for testing a memory

Memory device with data line steering and bitline redundancy

Two-dimensional redundancy calculation

Dram CAM cell with hidden refresh

Multi-ported memory with asynchronous and synchronous protocol

Method and apparatus for real time two dimensional redundancy alloc...

Enhanced built-in self-test circuit and method

Method and apparatus for real time two dimensional redundancy alloc...

Memory array built-in self test circuit for testing multi-port memo...

Memory array built-in self-test circuit having a programmable patte...

Test converage of embedded memories on semiconductor substrates

Memory array built-in self-test circuit having a programmable patte...

Method and apparatus to determine erroneous value in memory cells u...

Rapid compare of two binary numbers

Using one memory to supply addresses to an associated memory during...

Using one memory to supply addresses to an associated memory during...

BIST tester for multiple memories

Apparatus and method for real time data error capture and compressi...

Self calibrating timing circuit

Patents Applicationslast 30 patents

MULTIPLE USES FOR BIST TEST LATCHES

Multiple uses for bist test latches

Methods and apparatus for testing a memory

Memory device with data line steering and bitline redundancy

Two-dimensional redundancy calculation

DRAM CAM CELL WITH HIDDEN REFRESH