Garry P. Epps

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 8,665,875
- Issue date Mar 4, 2014
- Oracle International Corporation
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 8,571,024
- Issue date Oct 29, 2013
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 8,018,937
- Issue date Sep 13, 2011
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Instrumenting packet flows
- Patent number 8,000,251
- Issue date Aug 16, 2011
- Cisco Technology, Inc.
- Garry Paul Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Buffering schemes for optical packet processing
- Patent number 7,881,617
- Issue date Feb 1, 2011
- Cisco Technology, Inc.
- Earl T. Cohen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,864,791
- Issue date Jan 4, 2011
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optical data synchronization scheme
- Patent number 7,835,649
- Issue date Nov 16, 2010
- Cisco Technology, Inc.
- Garry Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,809,009
- Issue date Oct 5, 2010
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,792,027
- Issue date Sep 7, 2010
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,729,351
- Issue date Jun 1, 2010
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,715,419
- Issue date May 11, 2010
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,643,486
- Issue date Jan 5, 2010
- Cisco Technology, Inc.
- David Belz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed hardware implementation of RED congestion control algorithm
- Patent number 7,554,907
- Issue date Jun 30, 2009
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Port adapter for high-bandwidth bus
- Patent number 7,433,988
- Issue date Oct 7, 2008
- Cisco Technology, Inc.
- David Doak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Port adapter for high-bandwidth bus
- Patent number 7,310,695
- Issue date Dec 18, 2007
- Cisco Technology, Inc.
- Garry P. Epps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous pipelined switch using serial transmission
- Patent number 7,286,525
- Issue date Oct 23, 2007
- Cisco Technology, Inc.
- Michael Laor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,177,276
- Issue date Feb 13, 2007
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Port adapter for high-bandwidth bus
- Patent number 7,111,102
- Issue date Sep 19, 2006
- Cisco Technology, Inc.
- David Doak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 6,980,552
- Issue date Dec 27, 2005
- Cisco Technology, Inc.
- David Belz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 6,977,930
- Issue date Dec 20, 2005
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed hardware implementation of red congestion control algorithm
- Patent number 6,813,243
- Issue date Nov 2, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed hardware implementation of MDRR algorithm over a large n...
- Patent number 6,778,546
- Issue date Aug 17, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible DMA engine for packet header modification
- Patent number 6,731,644
- Issue date May 4, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible engine and data structure for packet header processing
- Patent number 6,721,316
- Issue date Apr 13, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronous pipelined switch using serial transmission
- Patent number 6,424,649
- Issue date Jul 23, 2002
- Cisco Technology, Inc.
- Michael Laor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Pipelined Packet Switching And Queuing Architecture
- Publication number 20120314707
- Publication date Dec 13, 2012
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PIPELINED PACKET SWITCHING AND QUEUING ARCHITECTURE
- Publication number 20110064084
- Publication date Mar 17, 2011
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined Packet Switching and Queuing Architecture
- Publication number 20080117913
- Publication date May 22, 2008
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Port adapter for high-bandwidth bus
- Publication number 20070283073
- Publication date Dec 6, 2007
- David Doak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffering schemes for optical packet processing
- Publication number 20070201870
- Publication date Aug 30, 2007
- Earl T. Cohen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Optical data synchronization scheme
- Publication number 20070201877
- Publication date Aug 30, 2007
- Garry Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20070195761
- Publication date Aug 23, 2007
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20070195773
- Publication date Aug 23, 2007
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20070195778
- Publication date Aug 23, 2007
- Cisco Technology, Inc.
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20070195777
- Publication date Aug 23, 2007
- Mohammed I. Tatar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Port adapter for high-bandwidth bus
- Publication number 20060277346
- Publication date Dec 7, 2006
- David Doak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20060050690
- Publication date Mar 9, 2006
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20060039374
- Publication date Feb 23, 2006
- David Belz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Port adapter for high-bandwidth bus
- Publication number 20050149651
- Publication date Jul 7, 2005
- David Doak
- G06 - COMPUTING CALCULATING COUNTING

Garry P. Epps

Person

Patents Grantslast 30 patents

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Instrumenting packet flows

Buffering schemes for optical packet processing

Pipelined packet switching and queuing architecture

Optical data synchronization scheme

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

High-speed hardware implementation of RED congestion control algorithm

Port adapter for high-bandwidth bus

Port adapter for high-bandwidth bus

Synchronous pipelined switch using serial transmission

Pipelined packet switching and queuing architecture

Port adapter for high-bandwidth bus

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

High-speed hardware implementation of red congestion control algorithm

High-speed hardware implementation of MDRR algorithm over a large n...

Flexible DMA engine for packet header modification

Flexible engine and data structure for packet header processing

Synchronous pipelined switch using serial transmission

Patents Applicationslast 30 patents

Pipelined Packet Switching And Queuing Architecture

PIPELINED PACKET SWITCHING AND QUEUING ARCHITECTURE

Pipelined Packet Switching and Queuing Architecture

Port adapter for high-bandwidth bus

Buffering schemes for optical packet processing

Optical data synchronization scheme

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Port adapter for high-bandwidth bus

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Port adapter for high-bandwidth bus