GARY HAMMOND

Person

FORT COLLINS, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performance in a virtualization architecture with a processor abstr...
- Patent number 8,214,830
- Issue date Jul 3, 2012
- Intel Corporation
- Hin L. Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing an advanced load address table for memory disambiguation...
- Patent number 7,441,107
- Issue date Oct 21, 2008
- Intel Corporation
- Gary N. Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to provide a source operand for an instruction...
- Patent number 7,395,415
- Issue date Jul 1, 2008
- Intel Corporation
- Gary Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decomposing architectural operation into speculative and architectu...
- Patent number 7,392,369
- Issue date Jun 24, 2008
- Intel Corporation
- Jeffery J. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing virtual addresses
- Patent number 7,383,374
- Issue date Jun 3, 2008
- Intel Corporation
- Koichi Yamada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resolving all previous potentially excepting architectural operatio...
- Patent number 7,330,963
- Issue date Feb 12, 2008
- Intel Corporation
- Jeffery J. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for lowering the die temperature of a micropro...
- Patent number 7,263,567
- Issue date Aug 28, 2007
- Intel Corporation
- Ganesh Subramaniyam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ordering scheme with architectural operation decomposed into result...
- Patent number 7,062,636
- Issue date Jun 13, 2006
- Intel Corporation
- Jeffery J. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible mechanism for enforcing coherency among caching structures
- Patent number 6,711,653
- Issue date Mar 23, 2004
- Intel Corporation
- Nhon Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast exception processing
- Patent number 6,625,693
- Issue date Sep 23, 2003
- Intel Corporation
- Ken Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual memory mapping using region-based page tables
- Patent number 6,604,184
- Issue date Aug 5, 2003
- Intel Corporation
- Achmed R. Zahir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing a computer system into a sleeping state
- Patent number 6,584,573
- Issue date Jun 24, 2003
- Intel Corporation
- Russ Wunderlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Article for providing event handling functionality in a processor s...
- Patent number 6,584,558
- Issue date Jun 24, 2003
- Intel Corporation
- Gary Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TLB using region ID prevalidation
- Patent number 6,560,689
- Issue date May 6, 2003
- Intel Corporation
- Gregory S. Mathews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microcode upgrade and special function support by executing RISC in...
- Patent number 6,542,981
- Issue date Apr 1, 2003
- Intel Corporation
- Nazar Abbas Zaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE...
- Patent number 6,430,657
- Issue date Aug 6, 2002
- Institute for the Development of Emerging Architecture L.L.C.
- Millind Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a virtual hashed page table
- Patent number 6,430,670
- Issue date Aug 6, 2002
- Hewlett-Packard Co.
- William R. Bryg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for pre-validating regions in a virtual addres...
- Patent number 6,408,373
- Issue date Jun 18, 2002
- Institute for the Development of Emerging Architectures, L.L.C.
- Stephen G. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing event handling functionality in...
- Patent number 6,408,386
- Issue date Jun 18, 2002
- Intel Corporation
- Gary Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing access to secure area of a cache
- Patent number 6,397,301
- Issue date May 28, 2002
- Intel Corporation
- Nhon T. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calculating a page table index from a virt...
- Patent number 6,393,544
- Issue date May 21, 2002
- Institute for the Development of Emerging Architectures, L.L.C.
- William R. Bryg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translation with/bypassing intermediate segmentation transl...
- Patent number 6,219,774
- Issue date Apr 17, 2001
- Intel Corporation
- Gary Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a virtual hashed page table
- Patent number 6,216,214
- Issue date Apr 10, 2001
- Institute for the Development of Emerging Architectures, L.L.C.
- William R. Bryg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing process switching in multiproce...
- Patent number 6,209,085
- Issue date Mar 27, 2001
- Intel Corporation
- Gary N. Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transferring data in a computer system
- Patent number 6,199,144
- Issue date Mar 6, 2001
- Intel Corporation
- Judge K. Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor event recognition
- Patent number 6,148,321
- Issue date Nov 14, 2000
- Intel Corporation
- Gary N. Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a load bias--load with intent to semaphore
- Patent number 6,128,706
- Issue date Oct 3, 2000
- Institute for the Development of Emerging Architectures, L.L.C.
- William R. Bryg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page table walker that uses at least one of a default page size and...
- Patent number 6,088,780
- Issue date Jul 11, 2000
- Institute for the Development of Emerging Architecture, L.L.C.
- Koichi Yamada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dependency matrix
- Patent number 6,065,105
- Issue date May 16, 2000
- Intel Corporation
- Nazar Zaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method for speculatively executing instructions from...
- Patent number 6,065,115
- Issue date May 16, 2000
- Intel Corporation
- Harshvardhan P. Sharangpani
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Performance In A Virtualization Architecture With A Processor Abstr...
- Publication number 20120240116
- Publication date Sep 20, 2012
- Hin L. Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtualizing memory management unit resources
- Publication number 20060224815
- Publication date Oct 5, 2006
- Koichi Yamada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for managing virtual addresses
- Publication number 20060224816
- Publication date Oct 5, 2006
- Koichi Yamada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor utilizing novel architectural ordering scheme
- Publication number 20060212682
- Publication date Sep 21, 2006
- Jeffery J. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor utilizing novel architectural ordering scheme
- Publication number 20060190705
- Publication date Aug 24, 2006
- Jeffery J. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor utilizing novel architectural ordering scheme
- Publication number 20060190706
- Publication date Aug 24, 2006
- Jeffery J. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performance in a virtualization architecture with a processor abstr...
- Publication number 20060161917
- Publication date Jul 20, 2006
- Hin L. Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to provide a source operand for an instruction...
- Publication number 20060095728
- Publication date May 4, 2006
- Gary Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Utilizing an advanced load address table for memory disambiguation...
- Publication number 20050149703
- Publication date Jul 7, 2005
- Gary N. Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible mechanism for enforcing coherency among caching structures
- Publication number 20050091459
- Publication date Apr 28, 2005
- Nhon Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor utilizing novel architectural ordering scheme
- Publication number 20040059898
- Publication date Mar 25, 2004
- Jeffery J. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL MEMORY MAPPING USING REGION-BASED PAGE TABLES
- Publication number 20030018876
- Publication date Jan 23, 2003
- ACHMED R. ZAHIR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Article for providing event handling functionality
- Publication number 20020120832
- Publication date Aug 29, 2002
- Intel Corporation
- Gary Hammond
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST EXCEPTION PROCESSING WITH MULTIPLE CACHED HANDLERS
- Publication number 20020052992
- Publication date May 2, 2002
- KEN ARORA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for pre-validating regions in a virtual addres...
- Publication number 20010021969
- Publication date Sep 13, 2001
- Stephen G. Burger
- G06 - COMPUTING CALCULATING COUNTING

GARY HAMMOND

Person

Patents Grantslast 30 patents

Performance in a virtualization architecture with a processor abstr...

Utilizing an advanced load address table for memory disambiguation...

Method and apparatus to provide a source operand for an instruction...

Decomposing architectural operation into speculative and architectu...

Method and apparatus for managing virtual addresses

Resolving all previous potentially excepting architectural operatio...

Method and apparatus for lowering the die temperature of a micropro...

Ordering scheme with architectural operation decomposed into result...

Flexible mechanism for enforcing coherency among caching structures

Fast exception processing

Virtual memory mapping using region-based page tables

Placing a computer system into a sleeping state

Article for providing event handling functionality in a processor s...

TLB using region ID prevalidation

Microcode upgrade and special function support by executing RISC in...

COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE...

Apparatus and method for a virtual hashed page table

Method and apparatus for pre-validating regions in a virtual addres...

Method and apparatus for providing event handling functionality in...

Preventing access to secure area of a cache

Method and apparatus for calculating a page table index from a virt...

Address translation with/bypassing intermediate segmentation transl...

Apparatus and method for a virtual hashed page table

Method and apparatus for performing process switching in multiproce...

Method and apparatus for transferring data in a computer system

Processor event recognition

Apparatus and method for a load bias--load with intent to semaphore

Page table walker that uses at least one of a default page size and...

Dependency matrix

Processor and method for speculatively executing instructions from...

Patents Applicationslast 30 patents

Performance In A Virtualization Architecture With A Processor Abstr...

Virtualizing memory management unit resources

Method and apparatus for managing virtual addresses

Processor utilizing novel architectural ordering scheme

Processor utilizing novel architectural ordering scheme

Processor utilizing novel architectural ordering scheme

Performance in a virtualization architecture with a processor abstr...

Method and apparatus to provide a source operand for an instruction...

Utilizing an advanced load address table for memory disambiguation...

Flexible mechanism for enforcing coherency among caching structures

Processor utilizing novel architectural ordering scheme

VIRTUAL MEMORY MAPPING USING REGION-BASED PAGE TABLES

Article for providing event handling functionality

FAST EXCEPTION PROCESSING WITH MULTIPLE CACHED HANDLERS

Method and apparatus for pre-validating regions in a virtual addres...