GARY K. YEAP

Person

SAN JOSE, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Automatic channel identification of high-bandwidth memory channels...
- Patent number 12,118,283
- Issue date Oct 15, 2024
- Synopsys, Inc.
- Xun Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic channel identification of high-bandwidth memory channels...
- Patent number 11,816,407
- Issue date Nov 14, 2023
- Synopsys, Inc.
- Xun Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methodology using Fin-FET transistors
- Patent number 10,922,467
- Issue date Feb 16, 2021
- Synopsys, Inc.
- Bohai Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methodology using Fin-FET transistors
- Patent number 10,817,636
- Issue date Oct 27, 2020
- Synopsys, Inc.
- Bohai Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cell placement technique for double patterning technology
- Patent number 8,726,215
- Issue date May 13, 2014
- Synopsys, Inc.
- John Jung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-chip co-design and co-optimization in three-dimensional integra...
- Patent number 8,392,870
- Issue date Mar 5, 2013
- Synopsys, Inc.
- Yifan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design-for-test-aware hierarchical design planning
- Patent number 7,937,677
- Issue date May 3, 2011
- Synopsys, Inc.
- Hung-Chun Chien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,961,916
- Issue date Nov 1, 2005
- Synopsys, Inc.
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,442,743
- Issue date Aug 27, 2002
- Monterey Design Systems
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrent placement of gates and associated...
- Patent number 6,385,760
- Issue date May 7, 2002
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design optimization using logical and physical information
- Patent number 6,286,128
- Issue date Sep 4, 2001
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for logic optimization for improving timing and congestion d...
- Patent number 6,192,508
- Issue date Feb 20, 2001
- Monterey Design Systems
- Sharad Malik
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODOLOGY USING FIN-FET TRANSISTORS
- Publication number 20190332737
- Publication date Oct 31, 2019
- Synopsys, Inc.
- Bohai LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODOLOGY USING FIN-FET TRANSISTORS
- Publication number 20160125116
- Publication date May 5, 2016
- Synopsys, Inc.
- Bohai LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Standard Cell Placement Technique For Double Patterning Technology
- Publication number 20130036397
- Publication date Feb 7, 2013
- Synopsys, Inc.
- John Jung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Two-Chip Co-Design And Co-Optimization In Three-Dimensional Integra...
- Publication number 20120198409
- Publication date Aug 2, 2012
- Synopsys, Inc.
- Yifan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design-For-Test-Aware Hierarchical Design Planning
- Publication number 20090288045
- Publication date Nov 19, 2009
- Synopsys, Inc.
- Hung-Chun Chien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement method for integrated circuit design using topo-clustering
- Publication number 20020138816
- Publication date Sep 26, 2002
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED...
- Publication number 20010047507
- Publication date Nov 29, 2001
- LAWRENCE PILEGGI
- G06 - COMPUTING CALCULATING COUNTING

GARY K. YEAP

Person

Patents Grantslast 30 patents

Automatic channel identification of high-bandwidth memory channels...

Automatic channel identification of high-bandwidth memory channels...

Methodology using Fin-FET transistors

Methodology using Fin-FET transistors

Standard cell placement technique for double patterning technology

Two-chip co-design and co-optimization in three-dimensional integra...

Design-for-test-aware hierarchical design planning

Placement method for integrated circuit design using topo-clustering

Placement method for integrated circuit design using topo-clustering

System and method for concurrent placement of gates and associated...

Method for design optimization using logical and physical information

Method for logic optimization for improving timing and congestion d...

Patents Applicationslast 30 patents

METHODOLOGY USING FIN-FET TRANSISTORS

METHODOLOGY USING FIN-FET TRANSISTORS

Standard Cell Placement Technique For Double Patterning Technology

Two-Chip Co-Design And Co-Optimization In Three-Dimensional Integra...

Design-For-Test-Aware Hierarchical Design Planning

Placement method for integrated circuit design using topo-clustering

SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED...